Merge pull request #69 from hzeller/use-design-top
In tests: Use $::env(DESIGN_TOP) where it isn't already.
diff --git a/design_introspection-plugin/tests/get_cells/get_cells.tcl b/design_introspection-plugin/tests/get_cells/get_cells.tcl
index 85cc897..4302b73 100644
--- a/design_introspection-plugin/tests/get_cells/get_cells.tcl
+++ b/design_introspection-plugin/tests/get_cells/get_cells.tcl
@@ -3,7 +3,7 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog get_cells.v
+read_verilog $::env(DESIGN_TOP).v
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
diff --git a/design_introspection-plugin/tests/get_nets/get_nets.tcl b/design_introspection-plugin/tests/get_nets/get_nets.tcl
index 2d3083a..93304bf 100644
--- a/design_introspection-plugin/tests/get_nets/get_nets.tcl
+++ b/design_introspection-plugin/tests/get_nets/get_nets.tcl
@@ -3,7 +3,7 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog get_nets.v
+read_verilog $::env(DESIGN_TOP).v
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
diff --git a/design_introspection-plugin/tests/get_pins/get_pins.tcl b/design_introspection-plugin/tests/get_pins/get_pins.tcl
index e352df1..b2efcdc 100644
--- a/design_introspection-plugin/tests/get_pins/get_pins.tcl
+++ b/design_introspection-plugin/tests/get_pins/get_pins.tcl
@@ -3,7 +3,7 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog get_pins.v
+read_verilog $::env(DESIGN_TOP).v
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.tcl b/design_introspection-plugin/tests/get_ports/get_ports.tcl
index f82305a..71df0a0 100644
--- a/design_introspection-plugin/tests/get_ports/get_ports.tcl
+++ b/design_introspection-plugin/tests/get_ports/get_ports.tcl
@@ -3,7 +3,7 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog get_ports.v
+read_verilog $::env(DESIGN_TOP).v
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
help get_ports
diff --git a/get_count-plugin/tests/simple/simple.tcl b/get_count-plugin/tests/simple/simple.tcl
index f933c94..8e006c8 100644
--- a/get_count-plugin/tests/simple/simple.tcl
+++ b/get_count-plugin/tests/simple/simple.tcl
@@ -1,7 +1,7 @@
yosys plugin -i get_count
yosys -import
-read_verilog -icells simple.v
+read_verilog -icells $::env(DESIGN_TOP).v
hierarchy -auto-top
set n [get_count -modules my_gate]
diff --git a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
index 223d9ec..43445c7 100644
--- a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
+++ b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
@@ -3,7 +3,7 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog set_clock_groups.v
+read_verilog $::env(DESIGN_TOP).v
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
diff --git a/selection-plugin/tests/counter/counter.tcl b/selection-plugin/tests/counter/counter.tcl
index 5475822..2411f8f 100644
--- a/selection-plugin/tests/counter/counter.tcl
+++ b/selection-plugin/tests/counter/counter.tcl
@@ -27,7 +27,7 @@
}
}
-read_verilog counter.v
+read_verilog $::env(DESIGN_TOP).v
read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
index fe1c07c..e347909 100644
--- a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
+++ b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
@@ -5,7 +5,7 @@
yosys -import
read_verilog $::env(DESIGN_TOP).v
-read_verilog VexRiscv_Lite.v
+read_verilog [file dirname [info script]]/VexRiscv_Lite.v
# -flatten is used to ensure that the output eblif has only one module.
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
