)]}'
{
  "commit": "ac62c6351f5a5885c10aae41c2a6f4d3a363ba5d",
  "tree": "a819f47d3ee8bab3f120ee96b95ca25fc88ca5a3",
  "parents": [
    "345fe14ee26f9de64170fffb00d7229ac6fe1864",
    "0251f7518b2b82547c8ff6ff7702d9593c6049e3"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Thu Feb 16 08:39:47 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Feb 16 08:39:47 2023 +0100"
  },
  "message": "Merge pull request #455 from antmicro/kr/imported_func\n\nsystemverilog-plugin: prefer full name in function calls",
  "tree_diff": []
}