tree a819f47d3ee8bab3f120ee96b95ca25fc88ca5a3
parent 345fe14ee26f9de64170fffb00d7229ac6fe1864
parent 0251f7518b2b82547c8ff6ff7702d9593c6049e3
author Kamil Rakoczy <krakoczy@antmicro.com> 1676533187 +0100
committer GitHub <noreply@github.com> 1676533187 +0100
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Merge pull request #455 from antmicro/kr/imported_func

systemverilog-plugin: prefer full name in function calls