commit ae92491a67fdbf77fb0c870b032edc6d3eded467
author Kamil Rakoczy <krakoczy@antmicro.com> Tue Feb 21 12:58:45 2023 +0100
committer GitHub <noreply@github.com> Tue Feb 21 12:58:45 2023 +0100
tree 11ed7f16ce81968cd96597f033cf234701129631
parent 93f80095a6b0498877d5e564ce12928ab9fd2bee
parent 4a9727c1d76615ec64fada5874e8b9a5a139a52c

Merge pull request #459 from antmicro/kr/remove_force_keep

systemverilog-plugin: remove force-keep attribute

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 0525f35..38c42a7 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -1934,10 +1934,6 @@
                 }
             }
         });
-        // TODO: setting keep attribute probably shouldn't be needed,
-        // but without this, modules that are generated in genscope are removed
-        // for now lets just add this attribute
-        module_node->attributes[ID::keep] = AST::AstNode::mkconst_int(1, false, 1);
         if (module_node->attributes.count(UhdmAst::partial())) {
             AST::AstNode *attr = module_node->attributes.at(UhdmAst::partial());
             if (attr->type == AST::AST_CONSTANT)