)]}'
{
  "commit": "af9d4b2353dd7953a630aaecf2c2f8eaa8559c80",
  "tree": "349e2a5cf3267bb69458c651b4195e0174a60748",
  "parents": [
    "c87f7b09eb0e29c9a2997a4ebd219d2622fb97ba"
  ],
  "author": {
    "name": "Tarachand Pagarani",
    "email": "tpagarani@quicklogic.com",
    "time": "Tue Mar 15 07:54:24 2022 -0700"
  },
  "committer": {
    "name": "Tarachand Pagarani",
    "email": "tpagarani@quicklogic.com",
    "time": "Tue Mar 15 07:54:24 2022 -0700"
  },
  "message": "update adder techmap to implement last 2 bits into regular logic\n\nSigned-off-by: Tarachand Pagarani \u003ctpagarani@quicklogic.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "25c69016ca9144a865671f26ed11b3af3456b507",
      "old_mode": 33188,
      "old_path": "ql-qlf-plugin/qlf_k6n10f/arith_map.v",
      "new_id": "c5dd2217ab6061e66c65b854d5f0c054a01c432a",
      "new_mode": 33188,
      "new_path": "ql-qlf-plugin/qlf_k6n10f/arith_map.v"
    },
    {
      "type": "modify",
      "old_id": "41443f403c6975bdbc16a60fd286accf977f4999",
      "old_mode": 33188,
      "old_path": "ql-qlf-plugin/tests/full_adder/full_adder.tcl",
      "new_id": "deef6b5351074a2da107465b9ff2e18ac72a09b4",
      "new_mode": 33188,
      "new_path": "ql-qlf-plugin/tests/full_adder/full_adder.tcl"
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}