tests: sdc: pll: have deterministic tests outputs
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
diff --git a/sdc-plugin/tests/get_clocks/get_clocks.golden.txt b/sdc-plugin/tests/get_clocks/get_clocks.golden.txt
index 5744ab5..13196ee 100644
--- a/sdc-plugin/tests/get_clocks/get_clocks.golden.txt
+++ b/sdc-plugin/tests/get_clocks/get_clocks.golden.txt
@@ -1,5 +1,5 @@
clk clk2 clk_int_1
-{$auto$clkbufmap.cc:262:execute$1845} clk clk2 clk_int_1
+clk clk2 clk_int_1 main_clkout0
clk2
clk_int_1
clk clk2 clk_int_1
diff --git a/sdc-plugin/tests/get_clocks/get_clocks.tcl b/sdc-plugin/tests/get_clocks/get_clocks.tcl
index 3dd8e23..71b3079 100644
--- a/sdc-plugin/tests/get_clocks/get_clocks.tcl
+++ b/sdc-plugin/tests/get_clocks/get_clocks.tcl
@@ -8,7 +8,7 @@
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
# Start flow after library reading
-synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -noclkbuf -run prepare:check
#synth_xilinx
# Read the design's timing constraints
diff --git a/sdc-plugin/tests/get_clocks/get_clocks.v b/sdc-plugin/tests/get_clocks/get_clocks.v
index 4218db5..1154245 100644
--- a/sdc-plugin/tests/get_clocks/get_clocks.v
+++ b/sdc-plugin/tests/get_clocks/get_clocks.v
@@ -39,11 +39,14 @@
.CLKOUT0(main_clkout0),
);
+ wire main_clkout0_bufg;
+ BUFG bufg (.I(main_clkout0), .O(main_clkout0_bufg));
+
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
- always @(posedge main_clkout0) begin
+ always @(posedge main_clkout0_bufg) begin
cnt2 <= cnt2 + 1;
end
diff --git a/sdc-plugin/tests/pll/pll.golden.sdc b/sdc-plugin/tests/pll/pll.golden.sdc
index 1a17ded..dc34210 100644
--- a/sdc-plugin/tests/pll/pll.golden.sdc
+++ b/sdc-plugin/tests/pll/pll.golden.sdc
@@ -1,3 +1,3 @@
-create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:262:execute\$1717
-create_clock -period 2.5 -waveform {0 1.25} \$auto\$clkbufmap.cc:262:execute\$1719
-create_clock -period 5 -waveform {1.25 3.75} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 10 -waveform {2.5 7.5} main_clkout0
+create_clock -period 2.5 -waveform {0 1.25} main_clkout1
+create_clock -period 5 -waveform {1.25 3.75} main_clkout2
diff --git a/sdc-plugin/tests/pll/pll.tcl b/sdc-plugin/tests/pll/pll.tcl
index 7db8970..c7318de 100644
--- a/sdc-plugin/tests/pll/pll.tcl
+++ b/sdc-plugin/tests/pll/pll.tcl
@@ -8,7 +8,7 @@
hierarchy -check -auto-top
# Start flow after library reading
-synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -noclkbuf -run prepare:check
# Read the design timing constraints
read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll/pll.v b/sdc-plugin/tests/pll/pll.v
index 7c0045c..b799dc3 100644
--- a/sdc-plugin/tests/pll/pll.v
+++ b/sdc-plugin/tests/pll/pll.v
@@ -18,9 +18,15 @@
wire fdce_0_out, fdce_1_out;
wire main_locked;
+ wire clk_ibuf;
+ IBUF ibuf_clk(.I(clk), .O(clk_ibuf));
+
+ wire clk_bufg;
+ BUFG bufg_clk(.I(clk_ibuf), .O(clk_bufg));
+
FDCE FDCE_0 (
.D (data_in),
- .C (clk),
+ .C (clk_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (fdce_0_out)
@@ -28,7 +34,7 @@
FDCE FDCE_1 (
.D (fdce_0_out),
- .C (clk),
+ .C (clk_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[0])
@@ -57,9 +63,17 @@
.LOCKED(main_locked)
);
+ wire main_clkout0_bufg;
+ wire main_clkout1_bufg;
+ wire main_clkout2_bufg;
+
+ BUFG bufg_clkout0 (.I(main_clkout0), .O(main_clkout0_bufg));
+ BUFG bufg_clkout1 (.I(main_clkout1), .O(main_clkout1_bufg));
+ BUFG bufg_clkout2 (.I(main_clkout2), .O(main_clkout2_bufg));
+
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
- .C (main_clkout0),
+ .C (main_clkout0_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[1])
@@ -67,7 +81,7 @@
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
- .C (main_clkout1),
+ .C (main_clkout1_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[2])
@@ -75,7 +89,7 @@
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
- .C (main_clkout1),
+ .C (main_clkout1_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[3])
@@ -83,7 +97,7 @@
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
- .C (main_clkout1),
+ .C (main_clkout1_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[4])
@@ -91,7 +105,7 @@
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
- .C (main_clkout2),
+ .C (main_clkout2_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[5])
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc
index 61f951a..597a2ef 100644
--- a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc
+++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc
@@ -1,3 +1,3 @@
-create_clock -period 9.99999 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1717
-create_clock -period 5 -waveform {-2.5 0} \$auto\$clkbufmap.cc:262:execute\$1719
-create_clock -period 2.5 -waveform {-1.875 -0.624999} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 9.99999 -waveform {0 5} main_clkout_x1
+create_clock -period 5 -waveform {-2.5 0} main_clkout_x2
+create_clock -period 2.5 -waveform {-1.875 -0.624999} main_clkout_x4
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
index b877a2d..87b05cd 100644
--- a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
+++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
@@ -8,7 +8,7 @@
hierarchy -check -auto-top
# Start flow after library reading
-synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -noclkbuf -run prepare:check
# Read the design timing constraints
read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_dangling_wires/pll_dangling_wires.golden.sdc b/sdc-plugin/tests/pll_dangling_wires/pll_dangling_wires.golden.sdc
index 1bd5952..6665821 100644
--- a/sdc-plugin/tests/pll_dangling_wires/pll_dangling_wires.golden.sdc
+++ b/sdc-plugin/tests/pll_dangling_wires/pll_dangling_wires.golden.sdc
@@ -1 +1 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1704
+create_clock -period 10 -waveform {0 5} main_clkout0
diff --git a/sdc-plugin/tests/pll_dangling_wires/pll_dangling_wires.tcl b/sdc-plugin/tests/pll_dangling_wires/pll_dangling_wires.tcl
index aa9d35e..de162b7 100644
--- a/sdc-plugin/tests/pll_dangling_wires/pll_dangling_wires.tcl
+++ b/sdc-plugin/tests/pll_dangling_wires/pll_dangling_wires.tcl
@@ -8,7 +8,7 @@
hierarchy -check -auto-top
# Start flow after library reading
-synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -noclkbuf -run prepare:check
# Read the design timing constraints
read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_div/pll_div.golden.sdc b/sdc-plugin/tests/pll_div/pll_div.golden.sdc
index fee281c..72b4513 100644
--- a/sdc-plugin/tests/pll_div/pll_div.golden.sdc
+++ b/sdc-plugin/tests/pll_div/pll_div.golden.sdc
@@ -1,3 +1,3 @@
-create_clock -period 20 -waveform {5 15} \$auto\$clkbufmap.cc:262:execute\$1717
-create_clock -period 5 -waveform {0 2.5} \$auto\$clkbufmap.cc:262:execute\$1719
-create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 20 -waveform {5 15} main_clkout0
+create_clock -period 5 -waveform {0 2.5} main_clkout1
+create_clock -period 10 -waveform {2.5 7.5} main_clkout2
diff --git a/sdc-plugin/tests/pll_div/pll_div.tcl b/sdc-plugin/tests/pll_div/pll_div.tcl
index bdce1f3..a556779 100644
--- a/sdc-plugin/tests/pll_div/pll_div.tcl
+++ b/sdc-plugin/tests/pll_div/pll_div.tcl
@@ -8,7 +8,7 @@
hierarchy -check -auto-top
# Start flow after library reading
-synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -noclkbuf -run prepare:check
# Read the design timing constraints
read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.golden.sdc b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.golden.sdc
index 0eab91d..5dc7091 100644
--- a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.golden.sdc
+++ b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.golden.sdc
@@ -1,3 +1,3 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1717
-create_clock -period 5 -waveform {-2.5 0} \$auto\$clkbufmap.cc:262:execute\$1719
-create_clock -period 2.5 -waveform {-1.875 -0.625} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 10 -waveform {0 5} main_clkout_x1
+create_clock -period 5 -waveform {-2.5 0} main_clkout_x2
+create_clock -period 2.5 -waveform {-1.875 -0.625} main_clkout_x4
diff --git a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
index ceef986..c326630 100644
--- a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
+++ b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
@@ -8,7 +8,7 @@
hierarchy -check -auto-top
# Start flow after library reading
-synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -noclkbuf -run prepare:check
# Read the design timing constraints
read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_propagated/pll_propagated.golden.sdc b/sdc-plugin/tests/pll_propagated/pll_propagated.golden.sdc
index 5f1fc75..4bad809 100644
--- a/sdc-plugin/tests/pll_propagated/pll_propagated.golden.sdc
+++ b/sdc-plugin/tests/pll_propagated/pll_propagated.golden.sdc
@@ -1,8 +1,8 @@
-create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1715
-create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:262:execute\$1717
-create_clock -period 2.5 -waveform {0 1.25} \$auto\$clkbufmap.cc:262:execute\$1719
-create_clock -period 5 -waveform {1.25 3.75} \$auto\$clkbufmap.cc:262:execute\$1721
-create_clock -period 10 -waveform {0 5} \$techmap1617\FDCE_0.C
+create_clock -period 10 -waveform {0 5} clk_bufg
+create_clock -period 10 -waveform {0 5} clk_ibuf
create_clock -period 10 -waveform {2.5 7.5} main_clkout0
+create_clock -period 10 -waveform {2.5 7.5} main_clkout0_bufg
create_clock -period 2.5 -waveform {0 1.25} main_clkout1
+create_clock -period 2.5 -waveform {0 1.25} main_clkout1_bufg
create_clock -period 5 -waveform {1.25 3.75} main_clkout2
+create_clock -period 5 -waveform {1.25 3.75} main_clkout2_bufg
diff --git a/sdc-plugin/tests/pll_propagated/pll_propagated.tcl b/sdc-plugin/tests/pll_propagated/pll_propagated.tcl
index 46b8f8a..6f8d320 100644
--- a/sdc-plugin/tests/pll_propagated/pll_propagated.tcl
+++ b/sdc-plugin/tests/pll_propagated/pll_propagated.tcl
@@ -8,7 +8,7 @@
hierarchy -check -auto-top
# Start flow after library reading
-synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -noclkbuf -run prepare:check
# Read the design timing constraints
read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_propagated/pll_propagated.v b/sdc-plugin/tests/pll_propagated/pll_propagated.v
index 7c0045c..b799dc3 100644
--- a/sdc-plugin/tests/pll_propagated/pll_propagated.v
+++ b/sdc-plugin/tests/pll_propagated/pll_propagated.v
@@ -18,9 +18,15 @@
wire fdce_0_out, fdce_1_out;
wire main_locked;
+ wire clk_ibuf;
+ IBUF ibuf_clk(.I(clk), .O(clk_ibuf));
+
+ wire clk_bufg;
+ BUFG bufg_clk(.I(clk_ibuf), .O(clk_bufg));
+
FDCE FDCE_0 (
.D (data_in),
- .C (clk),
+ .C (clk_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (fdce_0_out)
@@ -28,7 +34,7 @@
FDCE FDCE_1 (
.D (fdce_0_out),
- .C (clk),
+ .C (clk_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[0])
@@ -57,9 +63,17 @@
.LOCKED(main_locked)
);
+ wire main_clkout0_bufg;
+ wire main_clkout1_bufg;
+ wire main_clkout2_bufg;
+
+ BUFG bufg_clkout0 (.I(main_clkout0), .O(main_clkout0_bufg));
+ BUFG bufg_clkout1 (.I(main_clkout1), .O(main_clkout1_bufg));
+ BUFG bufg_clkout2 (.I(main_clkout2), .O(main_clkout2_bufg));
+
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
- .C (main_clkout0),
+ .C (main_clkout0_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[1])
@@ -67,7 +81,7 @@
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
- .C (main_clkout1),
+ .C (main_clkout1_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[2])
@@ -75,7 +89,7 @@
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
- .C (main_clkout1),
+ .C (main_clkout1_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[3])
@@ -83,7 +97,7 @@
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
- .C (main_clkout1),
+ .C (main_clkout1_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[4])
@@ -91,7 +105,7 @@
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
- .C (main_clkout2),
+ .C (main_clkout2_bufg),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[5])
