SDC: Update existing clock instead of replacing with new
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/buffers.cc b/sdc-plugin/buffers.cc
index 072efe1..125b549 100644
--- a/sdc-plugin/buffers.cc
+++ b/sdc-plugin/buffers.cc
@@ -18,7 +18,6 @@
#include "buffers.h"
const std::vector<std::string> Pll::inputs = {"CLKIN1", "CLKIN2"};
-const std::vector<std::string> Pll::outputs = {"CLKOUT0", "CLKOUT1", "CLKOUT2",
- "CLKOUT3", "CLKOUT4", "CLKOUT5"};
-const float Pll::delay = 1;
+const std::vector<std::string> Pll::outputs = {"CLKOUT0", "CLKOUT1", "CLKOUT2", "CLKOUT3", "CLKOUT4", "CLKOUT5"};
+const float Pll::delay = 0;
const std::string Pll::name = "PLLE2_ADV";
diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index c7f6e9d..dc1dbcf 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -33,9 +33,11 @@
[&](Clock& clock) { return clock.Name() == name; });
if (clock != clocks_.end()) {
log("Clock %s already exists and will be overwritten\n", name.c_str());
- clocks_.erase(clock);
+ clock->UpdateClock(wire, period, rising_edge, falling_edge);
+ } else {
+ log("Inserting clock %s with period %f, r:%f, f:%f\n", name.c_str(), period, rising_edge, falling_edge);
+ clocks_.emplace_back(name, wire, period, rising_edge, falling_edge);
}
- clocks_.emplace_back(name, wire, period, rising_edge, falling_edge);
}
void Clocks::AddClock(Clock& clock) {
@@ -145,9 +147,11 @@
Buffer buffer) {
auto clock_wires = clock.GetClockWires();
for (auto clock_wire : clock_wires) {
- log("%s\n", clock_wire->name.c_str());
- auto buf_wires = pass->FindSinkWiresForCellType(clock_wire, buffer.name,
- buffer.output);
+#ifdef SDC_DEBUG
+ log("Clock wire %s\n", RTLIL::unescape_id(clock_wire->name).c_str());
+#endif
+ auto buf_wires = pass->FindSinkWiresForCellType(
+ clock_wire, buffer.name, buffer.output);
int path_delay(0);
for (auto wire : buf_wires) {
#ifdef SDC_DEBUG
@@ -204,6 +208,18 @@
}
}
+void Clock::UpdateClock(RTLIL::Wire* wire, float period, float rising_edge, float falling_edge) {
+ UpdateWires(wire);
+ UpdatePeriod(period);
+ UpdateWaveform(rising_edge, falling_edge);
+}
+
+void Clock::UpdateWires(RTLIL::Wire* wire) {
+ if (std::find(clock_wires_.begin(), clock_wires_.end(), wire) == clock_wires_.end()) {
+ clock_wires_.push_back(wire);
+ }
+}
+
void Clock::UpdatePeriod(float period) {
period_ = period;
rising_edge_ = 0;
diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h
index 97fe75c..d98d5b4 100644
--- a/sdc-plugin/clocks.h
+++ b/sdc-plugin/clocks.h
@@ -41,8 +41,7 @@
float Period() { return period_; }
float RisingEdge() { return rising_edge_; }
float FallingEdge() { return falling_edge_; }
- void UpdatePeriod(float period);
- void UpdateWaveform(float rising_edge, float falling_edge);
+ void UpdateClock(RTLIL::Wire* wire, float period, float rising_edge, float falling_edge);
private:
std::string name_;
@@ -50,6 +49,10 @@
float period_;
float rising_edge_;
float falling_edge_;
+
+ void UpdateWires(RTLIL::Wire* wire);
+ void UpdatePeriod(float period);
+ void UpdateWaveform(float rising_edge, float falling_edge);
};
class Clocks {
diff --git a/sdc-plugin/sdc.cc b/sdc-plugin/sdc.cc
index d158e5b..73eec15 100644
--- a/sdc-plugin/sdc.cc
+++ b/sdc-plugin/sdc.cc
@@ -104,6 +104,7 @@
RTLIL::Design* design) override {
size_t argidx;
std::string name;
+ bool is_waveform_specified(false);
float rising_edge(0);
float falling_edge(0);
float period(0);
@@ -126,6 +127,7 @@
[](char c) { return c != '{' or c != '}'; });
std::stringstream ss(edges);
ss >> rising_edge >> falling_edge;
+ is_waveform_specified = true;
continue;
}
break;
@@ -159,6 +161,10 @@
if (name.empty()) {
name = RTLIL::unescape_id(selected_wires.at(0)->name);
}
+ if (!is_waveform_specified) {
+ rising_edge = 0;
+ falling_edge = period / 2;
+ }
clocks_.AddClock(name, selected_wires, period, rising_edge,
falling_edge);
log("Created clock %s with period %f, waveform {%f %f}\n", name.c_str(),
