)]}'
{
  "commit": "b4b3bd8c0d19be10ed2c95dda5134e2b897f6b1b",
  "tree": "68a3e5a557f8cf439bce4a1579a5364b74844e6d",
  "parents": [
    "a08c529a86a525fc4278221a5599a2e783c8105e"
  ],
  "author": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Thu May 11 17:53:49 2023 +0200"
  },
  "committer": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Fri May 12 12:43:38 2023 +0200"
  },
  "message": "do not get value size of a constant from its typespec\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "94736fe6327dc90e7bd73bc150a44fda69756fcd",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "e32be89d89603b8bf4cce1988089ca5dd02f85b9",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}