)]}'
{
  "commit": "b64bd44b5e2987a29e120a32e0d81b1f4e5b4c72",
  "tree": "b83f91803c06bd5cf21e4546711570cb23517b8e",
  "parents": [
    "eba2751f62b0af673955da0c3d6b6e32c6fe12cb"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Mon Apr 03 12:30:56 2023 +0200"
  },
  "committer": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Wed Apr 05 16:01:03 2023 +0200"
  },
  "message": "systemverilog-plugin: Change the way Yosys::AST:: members are called\n\nSigned-off-by: Magdalena Andrys \u003cmandrys@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2f60ce4c8dab26bab1d6d225cbd9d382b63bb97a",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/third_party/yosys/simplify.cc",
      "new_id": "47d04f77eada2c7f43f40a4fb73101f6411ac079",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/third_party/yosys/simplify.cc"
    }
  ]
}