systemverilog: Fix signed wire handling
Signed-off-by: Magdalena Andrys <mandrys@antmicro.com>
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 1c62f28..3737d9a 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -1397,7 +1397,7 @@
if (child->type == AST::AST_MEMORY)
child->type = AST::AST_WIRE;
}
- child->is_signed = (*it)->is_signed;
+ child->is_signed = child->is_signed || (*it)->is_signed;
if (!(*it)->children.empty() && child->children.empty()) {
// This is a bit ugly, but if the child we're replacing has children and
// our node doesn't, we copy its children to not lose any information
@@ -3968,7 +3968,7 @@
current_node->children = std::move(node->children);
}
}
- current_node->is_signed = node->is_signed;
+ current_node->is_signed = current_node->is_signed || node->is_signed;
delete node;
}
});
