)]}'
{
  "commit": "b9c98a1d48905eb7d920971c60055088ee26eb12",
  "tree": "7eecc64dddf29590f0dd99ae6f5b6638a0ba649b",
  "parents": [
    "e81b0c14d554fbf9cef14dd33155f441242d5ca2"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Wed Nov 16 14:59:50 2022 +0100"
  },
  "committer": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Tue Jan 10 14:30:41 2023 +0100"
  },
  "message": "systemverilog: Fix signed wire handling\n\nSigned-off-by: Magdalena Andrys \u003cmandrys@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1c62f28e2cf4cdf73ef552bdb4d711b3944055cd",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "3737d9ac62ef3a95f9d9f59f716df6183a7f40a3",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}