commit bf5383e7d66840ee10cb4ad8377a8c2952ffa84d
author Magdalena Andrys <mandrys@antmicro.com> Fri Mar 24 15:39:53 2023 +0100
committer Magdalena Andrys <mandrys@antmicro.com> Wed Apr 05 15:57:50 2023 +0200
tree 5ca8b8a00444376e971ea467ca6507da4ebbc83a
parent fa22fa827d0b67570a64e5bcd36f266e774f979c

systemverilog-plugin: Update Makefile

Signed-off-by: Magdalena Andrys <mandrys@antmicro.com>

systemverilog-plugin/Makefile

diff --git a/systemverilog-plugin/Makefile b/systemverilog-plugin/Makefile
index af5320d..a72cb8f 100644
--- a/systemverilog-plugin/Makefile
+++ b/systemverilog-plugin/Makefile
@@ -22,7 +22,8 @@
           uhdmcommonfrontend.cc \
           uhdmsurelogastfrontend.cc \
           uhdmastreport.cc \
-          third_party/yosys/const2ast.cc
+          third_party/yosys/const2ast.cc \
+          third_party/yosys/simplify.cc
 
 # Directory to search for Surelog and UHDM libraries
 UHDM_INSTALL_DIR ?= /usr/local