)]}'
{
  "commit": "bf5383e7d66840ee10cb4ad8377a8c2952ffa84d",
  "tree": "5ca8b8a00444376e971ea467ca6507da4ebbc83a",
  "parents": [
    "fa22fa827d0b67570a64e5bcd36f266e774f979c"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Fri Mar 24 15:39:53 2023 +0100"
  },
  "committer": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Wed Apr 05 15:57:50 2023 +0200"
  },
  "message": "systemverilog-plugin: Update Makefile\n\nSigned-off-by: Magdalena Andrys \u003cmandrys@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "af5320d3f399b8bc3483a6b019e0e5ff18988288",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/Makefile",
      "new_id": "a72cb8fbb50eba02fb7c238d964a0cea7b013524",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/Makefile"
    }
  ]
}