)]}'
{
  "commit": "c12a4b81e2536cb70001f730e68beb01a39a02a8",
  "tree": "82de70e9c96fefe7a5db8e46d762ee3445d3c533",
  "parents": [
    "dc9605ac5240ef96e91bc599a295b5f54a946d20"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Jun 06 13:06:39 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Jun 07 07:29:30 2023 +0200"
  },
  "message": "yosys-systemverilog: apply review comments\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "64b2203f9724791e4b9840648436b041d17bd0d3",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "d2475f4529e137ba8482e2ff26a6442cbd612c71",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}