| commit | c6eb4fc6f4fe0c21b31555377cf5a062733f5388 | [log] [tgz] |
|---|---|---|
| author | Pawel Czarnecki <pczarnecki@antmicro.com> | Thu Oct 13 16:03:43 2022 +0200 |
| committer | Pawel Czarnecki <pczarnecki@antmicro.com> | Thu Oct 13 16:05:27 2022 +0200 |
| tree | 3682a39ac80f0f2da1f0d345fb724c290bff8dd2 | |
| parent | 27208ce08200a5e89e3bd4f466bc68824df38c32 [diff] |
ql-qlf: k6n10f: ql_dsp_simd: change naming scheme RTLIL::Cell 'name' field contains paths to source verilog files. Assigning two of those as the name of a new DSP cell will likely cause generation of very long module names, especially when the path argument to 'read_verilog' is a long absolute path. Long module names will propagate to long net names through 'autoname' pass and cause readability issues in post-synthesis verilog. This change prevents that. Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
This repository contains plugins for Yosys developed as part of the F4PGA project.
Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a selection of objects. Additionally provides functions to convert selection on TCL lists.
Following commands are added with the plugin:
Writes out the design's fasm features based on the parameter annotations on a design cell.
The plugin adds the following command:
Implements a pass that integrates inverters into cells that have ports with the ‘invertible_pin’ attribute set.
The plugin adds the following command:
Reads the specified parameter on a selected object.
The plugin adds the following command:
QuickLogic IOB plugin annotates IO buffer cells with information from IO placement constraints. Used during synthesis for QuickLogic EOS-S3 architecture.
The plugin adds the following command:
QuickLogic QLF plugin extends Yosys with synthesis support for qlf_k4n8 and qlf_k6n10 architectures.
The plugin adds the following command:
Detailed help on the supported command(s) can be obtained by running help <command_name> in Yosys.
Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the complete SDC information.
The plugin adds the following commands:
Reads Xilinx Design Constraints (XDC) files and annotates the specified cells parameters with properties such as:
The plugin adds the following commands:
Reads SystemVerilog and UHDM files and processes them into yosys AST.
The plugin adds the following commands:
Detailed help on the supported command(s) can be obtained by running help <command_name> in Yosys.