diff --git a/params-plugin/tests/Makefile b/params-plugin/tests/Makefile
index a3f2ff3..eceb128 100644
--- a/params-plugin/tests/Makefile
+++ b/params-plugin/tests/Makefile
@@ -1,39 +1,12 @@
 TESTS = pll
+include $(shell pwd)/../../Makefile_test.common
 
-pll_verify = $(call compare_json,pll) && test $$(grep "PASS" pll/params.txt | wc -l) -eq 2
+json_test = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json
 
-all: $(TESTS)
-
-compare_json = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json
-
-define test_tpl =
-$(1): $(1)/$(1).json
-	$$($(1)_verify)
-	RETVAL=$$$$? ; \
-	if [ $$$$RETVAL -eq 0 ]; then \
-		echo "$(1) PASS"; \
-		true; \
-	else \
-		echo "$(1) FAIL"; \
-		false; \
-	fi
-
-$(1)/$(1).json: $(1)/$(1).v
-	cd $(1); \
-	PART_JSON=../xc7a35tcsg324-1.json \
-	OUT_JSON=$(1).json \
-	INPUT_XDC_FILE=$(1).xdc \
-	yosys -p "tcl $(1).tcl" $(1).v -l yosys.log
-
-update_$(1): $(1)/$(1).json
-	@python compare_output_json.py --json $$< --golden $(1)/$(1).golden.json --update
-
+define json_update =
+$(1)_update_json:
+	python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json --update
 endef
 
-$(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
+pll_verify = $(call json_test,pll) && test $$(grep "PASS" pll/pll.txt | wc -l) -eq 2
 
-update: $(foreach test,$(TESTS),update_$(test))
-
-
-clean:
-	rm -rf $(foreach test,$(TESTS),$(test)/$(test).json $(test)/$(test).eblif $(test)/$(test).txt $(test)/yosys.log)
diff --git a/params-plugin/tests/pll/pll.tcl b/params-plugin/tests/pll/pll.tcl
index f6a6bf8..cc6e7b3 100644
--- a/params-plugin/tests/pll/pll.tcl
+++ b/params-plugin/tests/pll/pll.tcl
@@ -4,6 +4,7 @@
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
 
+read_verilog $::env(DESIGN_TOP).v
 read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
@@ -14,7 +15,7 @@
 if {[llength $phase] != 2} {
 	error "Getparam should return a list with 2 elements"
 }
-set fp [open "params.txt" "w"]
+set fp [open "pll.txt" "w"]
 puts -nonewline $fp "Phase before: "
 if {$phase == $reference_phase} {
 	puts $fp "PASS"
@@ -25,7 +26,7 @@
 # Modify the phase parameter value on one of the PLLE2_ADV instances
 setparam -set CLKOUT2_PHASE [expr [lindex $phase 0] * 1000] top/PLLE2_ADV
 
-# Verify that the parameter has been correctly updated on the chosen instance 
+# Verify that the parameter has been correctly updated on the chosen instance
 set reference_phase [list 90000 70]
 set phase [getparam CLKOUT2_PHASE top/PLLE2_ADV_0 top/PLLE2_ADV]
 puts -nonewline $fp "Phase after: "
@@ -40,8 +41,8 @@
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -run prepare:check
 
 # Map Xilinx tech library to 7-series VPR tech library.
-read_verilog -lib ../techmaps/cells_sim.v
-techmap -map  ../techmaps/cells_map.v
+read_verilog -lib ./techmaps/cells_sim.v
+techmap -map  ./techmaps/cells_map.v
 
 # opt_expr -undriven makes sure all nets are driven, if only by the $undef
 # net.
@@ -52,5 +53,5 @@
 stat
 
 # Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json
 write_blif -attr -param -cname -conn pll.eblif
diff --git a/params-plugin/tests/techmaps/cells_map.v b/params-plugin/tests/pll/techmaps/cells_map.v
similarity index 100%
rename from params-plugin/tests/techmaps/cells_map.v
rename to params-plugin/tests/pll/techmaps/cells_map.v
diff --git a/params-plugin/tests/techmaps/cells_sim.v b/params-plugin/tests/pll/techmaps/cells_sim.v
similarity index 100%
rename from params-plugin/tests/techmaps/cells_sim.v
rename to params-plugin/tests/pll/techmaps/cells_sim.v
diff --git a/params-plugin/tests/xc7a35tcsg324-1.json b/params-plugin/tests/xc7a35tcsg324-1.json
deleted file mode 100644
index 602b949..0000000
--- a/params-plugin/tests/xc7a35tcsg324-1.json
+++ /dev/null
@@ -1,10 +0,0 @@
-{
-    "iobanks": {
-        "0": "X1Y78",
-        "14": "X1Y26",
-        "15": "X1Y78",
-        "16": "X1Y130",
-        "34": "X113Y26",
-        "35": "X113Y78"
-    }
-}