commit ca48b84dff04e82b2daf86207c6e4e226b356cb9
author Paweł Czarnecki <pczarnecki@antmicro.com> Wed Mar 16 09:14:04 2022 +0100
committer Paweł Czarnecki <pczarnecki@antmicro.com> Thu Apr 14 13:05:51 2022 +0200
tree 82c633902e906e2e6277f434ab58bdd8f15283bb
parent ccd5cc5017ec4388360addc1747ae1635fca3eca

ql-qlf: k6n10f: bram: fix cell assertion in synthesis tests

Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>

ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl
index 5e9379e..2a161c1 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl
@@ -13,7 +13,7 @@
 opt_clean
 stat
 write_verilog sim/bram_sdp_32x512_post_synth.v
-select -assert-count 1 t:TDP_BRAM36
+select -assert-count 1 t:TDP36K
 
 select -clear
 design -load bram_sdp
@@ -24,7 +24,7 @@
 opt_clean
 stat
 write_verilog sim/bram_sdp_16x1024_post_synth.v
-select -assert-count 1 t:TDP_BRAM36
+select -assert-count 1 t:TDP36K
 
 select -clear
 design -load bram_sdp
@@ -35,7 +35,7 @@
 opt_clean
 stat
 write_verilog sim/bram_sdp_8x2048_post_synth.v
-select -assert-count 1 t:TDP_BRAM36
+select -assert-count 1 t:TDP36K
 
 select -clear
 design -load bram_sdp
@@ -46,5 +46,5 @@
 opt_clean
 stat
 write_verilog sim/bram_sdp_4x4096_post_synth.v
-select -assert-count 1 t:TDP_BRAM36
+select -assert-count 1 t:TDP36K
 

ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl
index f3a5349..5fd14e4 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl
@@ -13,7 +13,7 @@
 opt_clean
 stat
 write_verilog sim/bram_tdp_32x512_post_synth.v
-select -assert-count 1 t:TDP_BRAM36
+select -assert-count 1 t:TDP36K
 
 select -clear
 design -load bram_tdp
@@ -24,7 +24,7 @@
 opt_clean
 stat
 write_verilog sim/bram_tdp_16x1024_post_synth.v
-select -assert-count 1 t:TDP_BRAM36
+select -assert-count 1 t:TDP36K
 
 select -clear
 design -load bram_tdp
@@ -35,7 +35,7 @@
 opt_clean
 stat
 write_verilog sim/bram_tdp_8x2048_post_synth.v
-select -assert-count 1 t:TDP_BRAM36
+select -assert-count 1 t:TDP36K
 
 select -clear
 design -load bram_tdp
@@ -46,5 +46,5 @@
 opt_clean
 stat
 write_verilog sim/bram_tdp_4x4096_post_synth.v
-select -assert-count 1 t:TDP_BRAM36
+select -assert-count 1 t:TDP36K