commit ca5bb9a2bab9e264d70eab71b1067ad27713afb2
author Mariusz Glebocki <mglebocki@antmicro.com> Wed Jan 04 13:56:43 2023 +0100
committer GitHub <noreply@github.com> Wed Jan 04 13:56:43 2023 +0100
tree 0f48176c7f4a82e8080f9c352ddc2f0774a20859
parent dfc1b7320867185427b21e16183d6075ea8fcd18
parent 36150950dcf2acf47af719008ec33c055a0b4bab

Merge pull request #430 from antmicro/rszc/fix-interface-members-types

systemverilog: Fix missing interface members' types

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 8f92ac6..1c62f28 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -2545,7 +2545,7 @@
     if (shared.top_nodes.find(type) != shared.top_nodes.end()) {
         // Was created before, fill missing
         elaboratedInterface = shared.top_nodes[type];
-        visit_one_to_many({vpiPort}, obj_h, [&](AST::AstNode *node) {
+        visit_one_to_many({vpiPort, vpiVariables}, obj_h, [&](AST::AstNode *node) {
             if (node) {
                 add_or_replace_child(elaboratedInterface, node);
             }