commit cab19a328d1630adf2f4c3503e653125473d6a09
author Kamil Rakoczy <krakoczy@antmicro.com> Wed Apr 05 14:04:02 2023 +0200
committer Kamil Rakoczy <krakoczy@antmicro.com> Tue Apr 11 10:39:03 2023 +0200
tree 8ecf4c49c151d07b94cd3fa015a8adfc571ebbf0
parent 382aabfc436fe6496c32e685143081ab376a6982

systemverilog-plugin: only convert custom ranges when they exist

This prevents overriding previously correctly set ranges

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 1d9689e..4292cfc 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -1199,7 +1199,9 @@
         break;
     case AST::AST_STRUCT_ITEM:
         AST_INTERNAL::current_scope[current_node->str] = current_node;
-        convert_packed_unpacked_range(current_node);
+        if (current_node->attributes.count(UhdmAst::packed_ranges()) || current_node->attributes.count(UhdmAst::unpacked_ranges())) {
+            convert_packed_unpacked_range(current_node);
+        }
         while (simplify(current_node, true, false, false, 1, -1, false, false)) {
         };
         break;