)]}'
{
  "commit": "cab19a328d1630adf2f4c3503e653125473d6a09",
  "tree": "8ecf4c49c151d07b94cd3fa015a8adfc571ebbf0",
  "parents": [
    "382aabfc436fe6496c32e685143081ab376a6982"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Apr 05 14:04:02 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Apr 11 10:39:03 2023 +0200"
  },
  "message": "systemverilog-plugin: only convert custom ranges when they exist\n\nThis prevents overriding previously correctly set ranges\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1d9689e5b653bb10392f6757686c9dc5fa47f5b3",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "4292cfcefe0b69121ff0d8542b5b1fe2686b054b",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}