)]}'
{
  "commit": "cb5d661136e8db1c875ad1fffde16830e266151a",
  "tree": "e83fc6e87e2b59e6beb8ccd1de72032e9de37626",
  "parents": [
    "7ac20f12050f2a4fb169358c1956995e87325cce"
  ],
  "author": {
    "name": "George Hilliard",
    "email": "thirtythreeforty@gmail.com",
    "time": "Tue Mar 01 22:58:35 2022 -0600"
  },
  "committer": {
    "name": "George Hilliard",
    "email": "thirtythreeforty@gmail.com",
    "time": "Tue Mar 01 23:09:11 2022 -0600"
  },
  "message": "Emit error when encountering assert/assume properties\n\nYosys doesn\u0027t have good handling of properties yet (see\nYosysHQ/yosys#3223).  In the meantime, SymbiYosys with the UHDM plugin\nwill happily prove this model \"correct\":\n\n    module wrong(input clk);\n        logic data;\n        always_comb data \u003c\u003d 0;\n        assert property( @(posedge clk) data );\n    endmodule\n\nThe `assert property` is silently dropped from the UHDM parse tree when\nit\u0027s converted to AST nodes, and the user\u0027s design has a bug but passes\nformal.  (Changing it to a clocked immediate assertion allows the solver\nto find a counterexample.)\n\nAt least, emit an error for this case.  Real support for SVA assertions\ncan be added.\n\nSigned-off-by: George Hilliard \u003cthirtythreeforty@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a08f513bf8d4b7f6a2c68dce462f935ea624aa51",
      "old_mode": 33188,
      "old_path": "uhdm-plugin/UhdmAst.cc",
      "new_id": "ba4d8bcfc5e3eab4c5fb6abeaddadab647bdb2d3",
      "new_mode": 33188,
      "new_path": "uhdm-plugin/UhdmAst.cc"
    }
  ]
}