Fixed simulation model for sh_dff, added missing techmap for _SHREG_DFF_P_
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index ded97d4..5da2aae 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -23,11 +23,11 @@
(* clkbuf_sink *)
input wire C
);
- parameter [0:0] INIT = 1'b0;
- initial Q = INIT;
+ initial Q <= 1'b0;
always @(posedge C)
- Q <= D;
+ Q <= D;
+
endmodule
(* abc9_box, lib_blackbox *)
diff --git a/ql-qlf-plugin/qlf_k6n10f/ffs_map.v b/ql-qlf-plugin/qlf_k6n10f/ffs_map.v
index fe665fa..c510457 100644
--- a/ql-qlf-plugin/qlf_k6n10f/ffs_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/ffs_map.v
@@ -105,3 +105,44 @@
latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
endmodule
+module \$__SHREG_DFF_P_ (D, Q, C);
+ input D;
+ input C;
+ output Q;
+
+ parameter DEPTH = 2;
+
+ reg [DEPTH-2:0] q;
+
+ genvar i;
+ generate for (i = 0; i < DEPTH; i = i + 1) begin: slice
+
+ // First in chain
+ generate if (i == 0) begin
+ sh_dff #() shreg_beg (
+ .Q(q[i]),
+ .D(D),
+ .C(C)
+ );
+ end endgenerate
+ // Middle in chain
+ generate if (i > 0 && i != DEPTH-1) begin
+ sh_dff #() shreg_mid (
+ .Q(q[i]),
+ .D(q[i-1]),
+ .C(C)
+ );
+ end endgenerate
+ // Last in chain
+ generate if (i == DEPTH-1) begin
+ sh_dff #() shreg_end (
+ .Q(Q),
+ .D(q[i-1]),
+ .C(C)
+ );
+ end endgenerate
+ end: slice
+ endgenerate
+
+endmodule
+
