ql-qlf: update sim modules and techmaps ql-qlf: apply license ql-qlf: apply clkbuf sink attributes ql-qlf: TDP36K: s/\t/ / ql-qlf: replace uram module with sram1024x18 ql-qlf: change ram_mode and fifo_mode from regs back to wires ql-qlf: bram sim: remove PL_ signals ql-qlf: bram sim: remove SCAN_ signals ql-qlf: k6n10f: sim: remove RAM_ID signal Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
diff --git a/ql-qlf-plugin/Makefile b/ql-qlf-plugin/Makefile index 30200bf..67a58e6 100644 --- a/ql-qlf-plugin/Makefile +++ b/ql-qlf-plugin/Makefile
@@ -49,7 +49,7 @@ $(QLF_K6N10F_DIR)/brams.txt \ $(QLF_K6N10F_DIR)/cells_sim.v \ $(QLF_K6N10F_DIR)/sram1024x18.v \ - $(QLF_K6N10F_DIR)/TDP18Kx18_FIFO.v \ + $(QLF_K6N10F_DIR)/TDP18K_FIFO.v \ $(QLF_K6N10F_DIR)/ufifo_ctl.v \ $(QLF_K6N10F_DIR)/ffs_map.v \ $(QLF_K6N10F_DIR)/dsp_map.v \
diff --git a/ql-qlf-plugin/qlf_k6n10f/TDP18K_FIFO.v b/ql-qlf-plugin/qlf_k6n10f/TDP18K_FIFO.v new file mode 100644 index 0000000..4179268 --- /dev/null +++ b/ql-qlf-plugin/qlf_k6n10f/TDP18K_FIFO.v
@@ -0,0 +1,341 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire +module TDP18K_FIFO ( + RMODE_A_i, + RMODE_B_i, + WMODE_A_i, + WMODE_B_i, + WEN_A_i, + WEN_B_i, + REN_A_i, + REN_B_i, + CLK_A_i, + CLK_B_i, + BE_A_i, + BE_B_i, + ADDR_A_i, + ADDR_B_i, + WDATA_A_i, + WDATA_B_i, + RDATA_A_o, + RDATA_B_o, + EMPTY_o, + EPO_o, + EWM_o, + UNDERRUN_o, + FULL_o, + FMO_o, + FWM_o, + OVERRUN_o, + FLUSH_ni, + FMODE_i, +); + parameter SYNC_FIFO_i = 1'b0; + parameter POWERDN_i = 1'b0; + parameter SLEEP_i = 1'b0; + parameter PROTECT_i = 1'b0; + parameter UPAF_i = 11'b0; + parameter UPAE_i = 11'b0; + + input wire [2:0] RMODE_A_i; + input wire [2:0] RMODE_B_i; + input wire [2:0] WMODE_A_i; + input wire [2:0] WMODE_B_i; + input wire WEN_A_i; + input wire WEN_B_i; + input wire REN_A_i; + input wire REN_B_i; + (* clkbuf_sink *) + input wire CLK_A_i; + (* clkbuf_sink *) + input wire CLK_B_i; + input wire [1:0] BE_A_i; + input wire [1:0] BE_B_i; + input wire [13:0] ADDR_A_i; + input wire [13:0] ADDR_B_i; + input wire [17:0] WDATA_A_i; + input wire [17:0] WDATA_B_i; + output reg [17:0] RDATA_A_o; + output reg [17:0] RDATA_B_o; + output wire EMPTY_o; + output wire EPO_o; + output wire EWM_o; + output wire UNDERRUN_o; + output wire FULL_o; + output wire FMO_o; + output wire FWM_o; + output wire OVERRUN_o; + input wire FLUSH_ni; + input wire FMODE_i; + reg [17:0] wmsk_a; + reg [17:0] wmsk_b; + wire [8:0] addr_a; + wire [8:0] addr_b; + reg [4:0] addr_a_d; + reg [4:0] addr_b_d; + wire [17:0] ram_rdata_a; + wire [17:0] ram_rdata_b; + reg [17:0] aligned_wdata_a; + reg [17:0] aligned_wdata_b; + wire ren_o; + wire [10:0] ff_raddr; + wire [10:0] ff_waddr; + wire [13:0] ram_addr_a; + wire [13:0] ram_addr_b; + wire [3:0] ram_waddr_a; + wire [3:0] ram_waddr_b; + wire initn; + wire smux_rclk; + wire smux_wclk; + wire real_fmode; + wire [3:0] raw_fflags; + reg [1:0] fifo_rmode; + reg [1:0] fifo_wmode; + wire smux_clk_a; + wire smux_clk_b; + wire ram_ren_a; + wire ram_ren_b; + wire ram_wen_a; + wire ram_wen_b; + wire cen_a; + wire cen_b; + wire cen_a_n; + wire cen_b_n; + wire ram_wen_a_n; + wire ram_wen_b_n; + localparam MODE_9 = 3'b001; + always @(*) begin + fifo_rmode = (RMODE_B_i == MODE_9 ? 2'b10 : 2'b01); + fifo_wmode = (WMODE_A_i == MODE_9 ? 2'b10 : 2'b01); + end + assign smux_clk_a = CLK_A_i; + assign smux_clk_b = CLK_B_i; + assign real_fmode = FMODE_i; + assign ram_ren_b = real_fmode ? ren_o : REN_B_i; + assign ram_wen_a = FMODE_i ? ~FULL_o & WEN_A_i : WEN_A_i; + assign ram_ren_a = FMODE_i ? 0 : REN_A_i; + assign ram_wen_b = FMODE_i ? 1'b0 : WEN_B_i; + assign cen_b = ram_ren_b | ram_wen_b; + assign cen_a = ram_ren_a | ram_wen_a; + assign ram_waddr_b = real_fmode ? {ff_raddr[0], 3'b000} : ADDR_B_i[3:0]; + assign ram_waddr_a = real_fmode ? {ff_waddr[0], 3'b000} : ADDR_A_i[3:0]; + assign ram_addr_b = real_fmode ? {ff_raddr[10:0], 3'h0} : {ADDR_B_i[13:4], addr_b_d[3:0]}; + assign ram_addr_a = real_fmode ? {ff_waddr[10:0], 3'h0} : {ADDR_A_i[13:4], addr_a_d[3:0]}; + always @(posedge CLK_A_i) addr_a_d[3:0] <= ADDR_A_i[3:0]; + always @(posedge CLK_B_i) addr_b_d[3:0] <= ADDR_B_i[3:0]; + assign cen_a_n = ~cen_a; + assign ram_wen_a_n = ~ram_wen_a; + assign cen_b_n = ~cen_b; + assign ram_wen_b_n = ~ram_wen_b; + + sram1024x18 uram( + .clk_a(smux_clk_a), + .cen_a(cen_a_n), + .wen_a(ram_wen_a_n), + .addr_a(ram_addr_a[13:4]), + .wmsk_a(wmsk_a), + .wdata_a(aligned_wdata_a), + .rdata_a(ram_rdata_a), + .clk_b(smux_clk_b), + .cen_b(cen_b_n), + .wen_b(ram_wen_b_n), + .addr_b(ram_addr_b[13:4]), + .wmsk_b(wmsk_b), + .wdata_b(aligned_wdata_b), + .rdata_b(ram_rdata_b) + ); + fifo_ctl #( + .ADDR_WIDTH(11), + .FIFO_WIDTH(2), + .DEPTH(6) + ) fifo_ctl( + .rclk(smux_clk_b), + .rst_R_n(FLUSH_ni), + .wclk(smux_clk_a), + .rst_W_n(FLUSH_ni), + .ren(REN_B_i), + .wen(ram_wen_a), + .sync(SYNC_FIFO_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL_o, FMO_o, FWM_o, OVERRUN_o, EMPTY_o, EPO_o, EWM_o, UNDERRUN_o}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF_i), + .upae(UPAE_i) + ); + localparam MODE_1 = 3'b101; + localparam MODE_18 = 3'b010; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : WDATA_MODE_SEL + if (ram_wen_a == 1) begin + case (WMODE_A_i) + MODE_18: begin + aligned_wdata_a = WDATA_A_i; + {wmsk_a[17], wmsk_a[15:8]} = (FMODE_i ? 9'h000 : (BE_A_i[1] ? 9'h000 : 9'h1ff)); + {wmsk_a[16], wmsk_a[7:0]} = (FMODE_i ? 9'h000 : (BE_A_i[0] ? 9'h000 : 9'h1ff)); + end + MODE_9: begin + aligned_wdata_a = {{2 {WDATA_A_i[16]}}, {2 {WDATA_A_i[7:0]}}}; + {wmsk_a[17], wmsk_a[15:8]} = (ram_waddr_a[3] ? 9'h000 : 9'h1ff); + {wmsk_a[16], wmsk_a[7:0]} = (ram_waddr_a[3] ? 9'h1ff : 9'h000); + end + MODE_4: begin + aligned_wdata_a = {2'b00, {4 {WDATA_A_i[3:0]}}}; + wmsk_a[17:16] = 2'b00; + wmsk_a[15:12] = (ram_waddr_a[3:2] == 2'b11 ? 4'h0 : 4'hf); + wmsk_a[11:8] = (ram_waddr_a[3:2] == 2'b10 ? 4'h0 : 4'hf); + wmsk_a[7:4] = (ram_waddr_a[3:2] == 2'b01 ? 4'h0 : 4'hf); + wmsk_a[3:0] = (ram_waddr_a[3:2] == 2'b00 ? 4'h0 : 4'hf); + end + MODE_2: begin + aligned_wdata_a = {2'b00, {8 {WDATA_A_i[1:0]}}}; + wmsk_a[17:16] = 2'b00; + wmsk_a[15:14] = (ram_waddr_a[3:1] == 3'b111 ? 2'h0 : 2'h3); + wmsk_a[13:12] = (ram_waddr_a[3:1] == 3'b110 ? 2'h0 : 2'h3); + wmsk_a[11:10] = (ram_waddr_a[3:1] == 3'b101 ? 2'h0 : 2'h3); + wmsk_a[9:8] = (ram_waddr_a[3:1] == 3'b100 ? 2'h0 : 2'h3); + wmsk_a[7:6] = (ram_waddr_a[3:1] == 3'b011 ? 2'h0 : 2'h3); + wmsk_a[5:4] = (ram_waddr_a[3:1] == 3'b010 ? 2'h0 : 2'h3); + wmsk_a[3:2] = (ram_waddr_a[3:1] == 3'b001 ? 2'h0 : 2'h3); + wmsk_a[1:0] = (ram_waddr_a[3:1] == 3'b000 ? 2'h0 : 2'h3); + end + MODE_1: begin + aligned_wdata_a = {2'b00, {16 {WDATA_A_i[0]}}}; + wmsk_a = 18'h0ffff; + wmsk_a[{1'b0, ram_waddr_a[3:0]}] = 0; + end + default: wmsk_a = 18'h3ffff; + endcase + end + else begin + aligned_wdata_a = 18'h00000; + wmsk_a = 18'h3ffff; + end + if (ram_wen_b == 1) + case (WMODE_B_i) + MODE_18: begin + aligned_wdata_b = WDATA_B_i; + {wmsk_b[17], wmsk_b[15:8]} = (BE_B_i[1] ? 9'h000 : 9'h1ff); + {wmsk_b[16], wmsk_b[7:0]} = (BE_B_i[0] ? 9'h000 : 9'h1ff); + end + MODE_9: begin + aligned_wdata_b = {{2 {WDATA_B_i[16]}}, {2 {WDATA_B_i[7:0]}}}; + {wmsk_b[17], wmsk_b[15:8]} = (ram_waddr_b[3] ? 9'h000 : 9'h1ff); + {wmsk_b[16], wmsk_b[7:0]} = (ram_waddr_b[3] ? 9'h1ff : 9'h000); + end + MODE_4: begin + aligned_wdata_b = {2'b00, {4 {WDATA_B_i[3:0]}}}; + wmsk_b[17:16] = 2'b00; + wmsk_b[15:12] = (ram_waddr_b[3:2] == 2'b11 ? 4'h0 : 4'hf); + wmsk_b[11:8] = (ram_waddr_b[3:2] == 2'b10 ? 4'h0 : 4'hf); + wmsk_b[7:4] = (ram_waddr_b[3:2] == 2'b01 ? 4'h0 : 4'hf); + wmsk_b[3:0] = (ram_waddr_b[3:2] == 2'b00 ? 4'h0 : 4'hf); + end + MODE_2: begin + aligned_wdata_b = {2'b00, {8 {WDATA_B_i[1:0]}}}; + wmsk_b[17:16] = 2'b00; + wmsk_b[15:14] = (ram_waddr_b[3:1] == 3'b111 ? 2'h0 : 2'h3); + wmsk_b[13:12] = (ram_waddr_b[3:1] == 3'b110 ? 2'h0 : 2'h3); + wmsk_b[11:10] = (ram_waddr_b[3:1] == 3'b101 ? 2'h0 : 2'h3); + wmsk_b[9:8] = (ram_waddr_b[3:1] == 3'b100 ? 2'h0 : 2'h3); + wmsk_b[7:6] = (ram_waddr_b[3:1] == 3'b011 ? 2'h0 : 2'h3); + wmsk_b[5:4] = (ram_waddr_b[3:1] == 3'b010 ? 2'h0 : 2'h3); + wmsk_b[3:2] = (ram_waddr_b[3:1] == 3'b001 ? 2'h0 : 2'h3); + wmsk_b[1:0] = (ram_waddr_b[3:1] == 3'b000 ? 2'h0 : 2'h3); + end + MODE_1: begin + aligned_wdata_b = {2'b00, {16 {WDATA_B_i[0]}}}; + wmsk_b = 18'h0ffff; + wmsk_b[{1'b0, ram_waddr_b[3:0]}] = 0; + end + default: wmsk_b = 18'h3ffff; + endcase + else begin + aligned_wdata_b = 18'b000000000000000000; + wmsk_b = 18'h3ffff; + end + end + always @(*) begin : RDATA_A_MODE_SEL + case (RMODE_A_i) + default: RDATA_A_o = 18'h00000; + MODE_18: RDATA_A_o = ram_rdata_a; + MODE_9: begin + {RDATA_A_o[17], RDATA_A_o[15:8]} = 9'h000; + {RDATA_A_o[16], RDATA_A_o[7:0]} = (ram_addr_a[3] ? {ram_rdata_a[17], ram_rdata_a[15:8]} : {ram_rdata_a[16], ram_rdata_a[7:0]}); + end + MODE_4: begin + RDATA_A_o[17:4] = 14'h0000; + case (ram_addr_a[3:2]) + 3: RDATA_A_o[3:0] = ram_rdata_a[15:12]; + 2: RDATA_A_o[3:0] = ram_rdata_a[11:8]; + 1: RDATA_A_o[3:0] = ram_rdata_a[7:4]; + 0: RDATA_A_o[3:0] = ram_rdata_a[3:0]; + endcase + end + MODE_2: begin + RDATA_A_o[17:2] = 16'h0000; + case (ram_addr_a[3:1]) + 7: RDATA_A_o[1:0] = ram_rdata_a[15:14]; + 6: RDATA_A_o[1:0] = ram_rdata_a[13:12]; + 5: RDATA_A_o[1:0] = ram_rdata_a[11:10]; + 4: RDATA_A_o[1:0] = ram_rdata_a[9:8]; + 3: RDATA_A_o[1:0] = ram_rdata_a[7:6]; + 2: RDATA_A_o[1:0] = ram_rdata_a[5:4]; + 1: RDATA_A_o[1:0] = ram_rdata_a[3:2]; + 0: RDATA_A_o[1:0] = ram_rdata_a[1:0]; + endcase + end + MODE_1: begin + RDATA_A_o[17:1] = 17'h00000; + RDATA_A_o[0] = ram_rdata_a[ram_addr_a[3:0]]; + end + endcase + end + always @(*) + case (RMODE_B_i) + default: RDATA_B_o = 18'h15566; + MODE_18: RDATA_B_o = ram_rdata_b; + MODE_9: begin + {RDATA_B_o[17], RDATA_B_o[15:8]} = 9'b000000000; + {RDATA_B_o[16], RDATA_B_o[7:0]} = (ram_addr_b[3] ? {ram_rdata_b[17], ram_rdata_b[15:8]} : {ram_rdata_b[16], ram_rdata_b[7:0]}); + end + MODE_4: + case (ram_addr_b[3:2]) + 3: RDATA_B_o[3:0] = ram_rdata_b[15:12]; + 2: RDATA_B_o[3:0] = ram_rdata_b[11:8]; + 1: RDATA_B_o[3:0] = ram_rdata_b[7:4]; + 0: RDATA_B_o[3:0] = ram_rdata_b[3:0]; + endcase + MODE_2: + case (ram_addr_b[3:1]) + 7: RDATA_B_o[1:0] = ram_rdata_b[15:14]; + 6: RDATA_B_o[1:0] = ram_rdata_b[13:12]; + 5: RDATA_B_o[1:0] = ram_rdata_b[11:10]; + 4: RDATA_B_o[1:0] = ram_rdata_b[9:8]; + 3: RDATA_B_o[1:0] = ram_rdata_b[7:6]; + 2: RDATA_B_o[1:0] = ram_rdata_b[5:4]; + 1: RDATA_B_o[1:0] = ram_rdata_b[3:2]; + 0: RDATA_B_o[1:0] = ram_rdata_b[1:0]; + endcase + MODE_1: RDATA_B_o[0] = ram_rdata_b[{1'b0, ram_addr_b[3:0]}]; + endcase +endmodule +`default_nettype none
diff --git a/ql-qlf-plugin/qlf_k6n10f/TDP18Kx18_FIFO.v b/ql-qlf-plugin/qlf_k6n10f/TDP18Kx18_FIFO.v deleted file mode 100644 index a68e88e..0000000 --- a/ql-qlf-plugin/qlf_k6n10f/TDP18Kx18_FIFO.v +++ /dev/null
@@ -1,363 +0,0 @@ -// Copyright 2020-2022 F4PGA Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 - -module TDP18K_FIFO ( - RMODE_A, - RMODE_B, - WMODE_A, - WMODE_B, - WEN_A, - WEN_B, - REN_A, - REN_B, - CLK_A, - CLK_B, - BE_A, - BE_B, - ADDR_A, - ADDR_B, - WDATA_A, - WDATA_B, - RDATA_A, - RDATA_B, - EMPTY, - EPO, - EWM, - UNDERRUN, - FULL, - FMO, - FWM, - OVERRUN, - FLUSH, - RAM_ID, - FMODE, - PL_INIT, - PL_ENA, - PL_WEN, - PL_REN, - PL_CLK, - PL_ADDR, - PL_DATA_IN, - PL_DATA_OUT -); - parameter SYNC_FIFO = 1'b0; - parameter POWERDN = 1'b0; - parameter SLEEP = 1'b0; - parameter PROTECT = 1'b0; - parameter UPAF = 11'b0; - parameter UPAE = 11'b0; - - input wire [2:0] RMODE_A; - input wire [2:0] RMODE_B; - input wire [2:0] WMODE_A; - input wire [2:0] WMODE_B; - input wire WEN_A; - input wire WEN_B; - input wire REN_A; - input wire REN_B; - (* clkbuf_sink *) - input wire CLK_A; - (* clkbuf_sink *) - input wire CLK_B; - input wire [1:0] BE_A; - input wire [1:0] BE_B; - input wire [13:0] ADDR_A; - input wire [13:0] ADDR_B; - input wire [17:0] WDATA_A; - input wire [17:0] WDATA_B; - output reg [17:0] RDATA_A; - output reg [17:0] RDATA_B; - output wire EMPTY; - output wire EPO; - output wire EWM; - output wire UNDERRUN; - output wire FULL; - output wire FMO; - output wire FWM; - output wire OVERRUN; - input wire FLUSH; - input wire [15:0] RAM_ID; - input wire FMODE; - input PL_INIT; - input PL_ENA; - input PL_WEN; - input PL_REN; - input PL_CLK; - input [31:0] PL_ADDR; - input [17:0] PL_DATA_IN; - output reg [17:0] PL_DATA_OUT; - reg [17:0] wmsk_a; - reg [17:0] wmsk_b; - wire [8:0] addr_a; - wire [8:0] addr_b; - reg [4:0] addr_a_d; - reg [4:0] addr_b_d; - wire [17:0] ram_rdata_a; - wire [17:0] ram_rdata_b; - reg [17:0] aligned_wdata_a; - reg [17:0] aligned_wdata_b; - wire ren_o; - wire [10:0] ff_raddr; - wire [10:0] ff_waddr; - wire [13:0] ram_addr_a; - wire [13:0] ram_addr_b; - wire [3:0] ram_waddr_a; - wire [3:0] ram_waddr_b; - wire preload; - wire my_id; - wire initn; - wire smux_rclk; - wire smux_wclk; - wire real_fmode; - wire [3:0] raw_fflags; - reg [1:0] fifo_rmode; - reg [1:0] fifo_wmode; - wire smux_clk_a; - wire smux_clk_b; - wire ram_ren_a; - wire ram_ren_b; - wire ram_wen_a; - wire ram_wen_b; - wire cen_a; - wire cen_b; - localparam MODE_9 = 3'b101; - always @(*) begin - fifo_rmode = (RMODE_B == MODE_9 ? 2'b10 : 2'b01); - fifo_wmode = (WMODE_A == MODE_9 ? 2'b10 : 2'b01); - end - assign my_id = (PL_ADDR[31:16] == RAM_ID) | PL_INIT; - assign preload = (PROTECT ? 1'b0 : my_id & PL_ENA); - assign smux_clk_a = (preload ? PL_CLK : CLK_A); - assign smux_clk_b = (preload ? 0 : (FMODE ? (SYNC_FIFO ? CLK_A : CLK_B) : CLK_B)); - assign real_fmode = (preload ? 1'b0 : FMODE); - assign ram_ren_b = (preload ? PL_REN : (real_fmode ? ren_o : REN_B)); - assign ram_wen_a = (preload ? PL_WEN : (FMODE ? ~FULL & WEN_A : WEN_A)); - assign ram_ren_a = (preload ? 1'b1 : (FMODE ? 0 : REN_A)); - assign ram_wen_b = (preload ? 1'b1 : (FMODE ? 1'b0 : WEN_B)); - assign cen_b = ram_ren_b | ram_wen_b; - assign cen_a = ram_ren_a | ram_wen_a; - assign ram_waddr_b = (preload ? 4'b0000 : (real_fmode ? {ff_raddr[0], 3'b000} : ADDR_B[3:0])); - assign ram_waddr_a = (preload ? 4'b0000 : (real_fmode ? {ff_waddr[0], 3'b000} : ADDR_A[3:0])); - assign ram_addr_b = (preload ? {PL_ADDR[10:0], 3'h0} : (real_fmode ? {ff_raddr[10:0], 3'h0} : {ADDR_B[13:4], addr_b_d[3:0]})); - assign ram_addr_a = (preload ? {PL_ADDR[10:0], 3'h0} : (real_fmode ? {ff_waddr[10:0], 3'b000} : {ADDR_A[13:4], addr_a_d[3:0]})); - always @(posedge CLK_A) addr_a_d[3:0] <= ADDR_A[3:0]; - always @(posedge CLK_B) addr_b_d[3:0] <= ADDR_B[3:0]; - sram1024x18 uram( - .clk_a(smux_clk_a), - .cen_a(~cen_a), - .wen_a(~ram_wen_a), - .addr_a(ram_addr_a[13:4]), - .wmsk_a(wmsk_a), - .wdata_a(aligned_wdata_a), - .rdata_a(ram_rdata_a), - .clk_b(smux_clk_b), - .cen_b(~cen_b), - .wen_b(~ram_wen_b), - .addr_b(ram_addr_b[13:4]), - .wmsk_b(wmsk_b), - .wdata_b(aligned_wdata_b), - .rdata_b(ram_rdata_b) - ); - fifo_ctl #( - .ADDR_WIDTH(11), - .FIFO_WIDTH(2) - ) fifo_ctl( - .rclk(smux_clk_b), - .rst_R_n(~FLUSH), - .wclk(smux_clk_a), - .rst_W_n(~FLUSH), - .ren(REN_B), - .wen(ram_wen_a), - .depth(3'b000), - .sync(SYNC_FIFO), - .rmode(fifo_rmode), - .wmode(fifo_wmode), - .ren_o(ren_o), - .fflags({FULL, FMO, FWM, OVERRUN, EMPTY, EPO, EWM, UNDERRUN}), - .raddr(ff_raddr), - .waddr(ff_waddr), - .upaf(UPAF), - .upae(UPAE) - ); - always @(*) begin : PRELOAD_DATA - if (preload & ram_ren_a) - PL_DATA_OUT = ram_rdata_a; - else - PL_DATA_OUT = PL_DATA_IN; - end - localparam MODE_1 = 3'b001; - localparam MODE_18 = 3'b110; - localparam MODE_2 = 3'b010; - localparam MODE_4 = 3'b100; - always @(*) begin : WDATA_MODE_SEL - if (ram_wen_a == 1) begin - if (preload) begin - aligned_wdata_a = PL_DATA_IN; - wmsk_a = 18'h00000; - end - else - case (WMODE_A) - MODE_18: begin - aligned_wdata_a = WDATA_A; - {wmsk_a[17], wmsk_a[15:8]} = (FMODE ? 9'h000 : (BE_A[1] ? 9'h000 : 9'h1ff)); - {wmsk_a[16], wmsk_a[7:0]} = (FMODE ? 9'h000 : (BE_A[0] ? 9'h000 : 9'h1ff)); - end - MODE_9: begin - aligned_wdata_a = {{2 {WDATA_A[8]}}, {2 {WDATA_A[7:0]}}}; - {wmsk_a[17], wmsk_a[15:8]} = (ram_waddr_a[3] ? 9'h000 : 9'h1ff); - {wmsk_a[16], wmsk_a[7:0]} = (ram_waddr_a[3] ? 9'h1ff : 9'h000); - end - MODE_4: begin - aligned_wdata_a = {2'b00, {4 {WDATA_A[3:0]}}}; - wmsk_a[17:16] = 2'b11; - wmsk_a[15:12] = (ram_waddr_a[3:2] == 2'b11 ? 4'h0 : 4'hf); - wmsk_a[11:8] = (ram_waddr_a[3:2] == 2'b10 ? 4'h0 : 4'hf); - wmsk_a[7:4] = (ram_waddr_a[3:2] == 2'b01 ? 4'h0 : 4'hf); - wmsk_a[3:0] = (ram_waddr_a[3:2] == 2'b00 ? 4'h0 : 4'hf); - end - MODE_2: begin - aligned_wdata_a = {2'b00, {8 {WDATA_A[1:0]}}}; - wmsk_a[17:16] = 2'b11; - wmsk_a[15:14] = (ram_waddr_a[3:1] == 3'b111 ? 2'h0 : 2'h3); - wmsk_a[13:12] = (ram_waddr_a[3:1] == 3'b110 ? 2'h0 : 2'h3); - wmsk_a[11:10] = (ram_waddr_a[3:1] == 3'b101 ? 2'h0 : 2'h3); - wmsk_a[9:8] = (ram_waddr_a[3:1] == 3'b100 ? 2'h0 : 2'h3); - wmsk_a[7:6] = (ram_waddr_a[3:1] == 3'b011 ? 2'h0 : 2'h3); - wmsk_a[5:4] = (ram_waddr_a[3:1] == 3'b010 ? 2'h0 : 2'h3); - wmsk_a[3:2] = (ram_waddr_a[3:1] == 3'b001 ? 2'h0 : 2'h3); - wmsk_a[1:0] = (ram_waddr_a[3:1] == 3'b000 ? 2'h0 : 2'h3); - end - MODE_1: begin - aligned_wdata_a = {2'b00, {16 {WDATA_A[0]}}}; - wmsk_a = 18'h3ffff; - wmsk_a[{1'b0, ram_waddr_a[3:0]}] = 0; - end - default: wmsk_a = 18'h3ffff; - endcase - end - else begin - aligned_wdata_a = 18'h00000; - wmsk_a = 18'h3ffff; - end - if (ram_wen_b == 1) - case (WMODE_B) - MODE_18: begin - aligned_wdata_b = WDATA_B; - {wmsk_b[17], wmsk_b[15:8]} = (BE_B[1] ? 9'h000 : 9'h1ff); - {wmsk_b[16], wmsk_b[7:0]} = (BE_B[0] ? 9'h000 : 9'h1ff); - end - MODE_9: begin - aligned_wdata_b = {{2 {WDATA_B[8]}}, {2 {WDATA_B[7:0]}}}; - {wmsk_b[17], wmsk_b[15:8]} = (ram_waddr_b[3] ? 9'h000 : 9'h1ff); - {wmsk_b[16], wmsk_b[7:0]} = (ram_waddr_b[3] ? 9'h1ff : 9'h000); - end - MODE_4: begin - aligned_wdata_b = {2'b00, {4 {WDATA_B[3:0]}}}; - wmsk_b[17:16] = 2'b11; - wmsk_b[15:12] = (ram_waddr_b[3:2] == 2'b11 ? 4'h0 : 4'hf); - wmsk_b[11:8] = (ram_waddr_b[3:2] == 2'b10 ? 4'h0 : 4'hf); - wmsk_b[7:4] = (ram_waddr_b[3:2] == 2'b01 ? 4'h0 : 4'hf); - wmsk_b[3:0] = (ram_waddr_b[3:2] == 2'b00 ? 4'h0 : 4'hf); - end - MODE_2: begin - aligned_wdata_b = {2'b00, {8 {WDATA_B[1:0]}}}; - wmsk_b[17:16] = 2'b11; - wmsk_b[15:14] = (ram_waddr_b[3:1] == 3'b111 ? 2'h0 : 2'h3); - wmsk_b[13:12] = (ram_waddr_b[3:1] == 3'b110 ? 2'h0 : 2'h3); - wmsk_b[11:10] = (ram_waddr_b[3:1] == 3'b101 ? 2'h0 : 2'h3); - wmsk_b[9:8] = (ram_waddr_b[3:1] == 3'b100 ? 2'h0 : 2'h3); - wmsk_b[7:6] = (ram_waddr_b[3:1] == 3'b011 ? 2'h0 : 2'h3); - wmsk_b[5:4] = (ram_waddr_b[3:1] == 3'b010 ? 2'h0 : 2'h3); - wmsk_b[3:2] = (ram_waddr_b[3:1] == 3'b001 ? 2'h0 : 2'h3); - wmsk_b[1:0] = (ram_waddr_b[3:1] == 3'b000 ? 2'h0 : 2'h3); - end - MODE_1: begin - aligned_wdata_b = {2'b00, {16 {WDATA_B[0]}}}; - wmsk_b = 18'h3ffff; - wmsk_b[{1'b0, ram_waddr_b[3:0]}] = 0; - end - default: wmsk_b = 18'h3ffff; - endcase - else begin - aligned_wdata_b = 18'b000000000000000000; - wmsk_b = 18'h3ffff; - end - end - always @(*) begin : RDATA_A_MODE_SEL - case (RMODE_A) - default: RDATA_A = 18'h00000; - MODE_18: RDATA_A = ram_rdata_a; - MODE_9: begin - RDATA_A[17:9] = 9'h000; - RDATA_A[8:0] = (ram_addr_a[3] ? {ram_rdata_a[17], ram_rdata_a[15:8]} : {ram_rdata_a[16], ram_rdata_a[7:0]}); - end - MODE_4: begin - RDATA_A[17:4] = 14'h0000; - case (ram_addr_a[3:2]) - 3: RDATA_A[3:0] = ram_rdata_a[15:12]; - 2: RDATA_A[3:0] = ram_rdata_a[11:8]; - 1: RDATA_A[3:0] = ram_rdata_a[7:4]; - 0: RDATA_A[3:0] = ram_rdata_a[3:0]; - endcase - end - MODE_2: begin - RDATA_A[17:2] = 16'h0000; - case (ram_addr_a[3:1]) - 7: RDATA_A[1:0] = ram_rdata_a[15:14]; - 6: RDATA_A[1:0] = ram_rdata_a[13:12]; - 5: RDATA_A[1:0] = ram_rdata_a[11:10]; - 4: RDATA_A[1:0] = ram_rdata_a[9:8]; - 3: RDATA_A[1:0] = ram_rdata_a[7:6]; - 2: RDATA_A[1:0] = ram_rdata_a[5:4]; - 1: RDATA_A[1:0] = ram_rdata_a[3:2]; - 0: RDATA_A[1:0] = ram_rdata_a[1:0]; - endcase - end - MODE_1: begin - RDATA_A[17:1] = 17'h00000; - RDATA_A[0] = ram_rdata_a[ram_addr_a[3:0]]; - end - endcase - end - always @(*) - case (RMODE_B) - default: RDATA_B = 18'h15566; - MODE_18: RDATA_B = ram_rdata_b; - MODE_9: begin - RDATA_B[17:9] = 1'sb1; - RDATA_B[8:0] = (ram_addr_b[3] ? {ram_rdata_b[17], ram_rdata_b[15:8]} : {ram_rdata_b[16], ram_rdata_b[7:0]}); - end - MODE_4: - case (ram_addr_b[3:2]) - 3: RDATA_B[3:0] = ram_rdata_b[15:12]; - 2: RDATA_B[3:0] = ram_rdata_b[11:8]; - 1: RDATA_B[3:0] = ram_rdata_b[7:4]; - 0: RDATA_B[3:0] = ram_rdata_b[3:0]; - endcase - MODE_2: - case (ram_addr_b[3:1]) - 7: RDATA_B[1:0] = ram_rdata_b[15:14]; - 6: RDATA_B[1:0] = ram_rdata_b[13:12]; - 5: RDATA_B[1:0] = ram_rdata_b[11:10]; - 4: RDATA_B[1:0] = ram_rdata_b[9:8]; - 3: RDATA_B[1:0] = ram_rdata_b[7:6]; - 2: RDATA_B[1:0] = ram_rdata_b[5:4]; - 1: RDATA_B[1:0] = ram_rdata_b[3:2]; - 0: RDATA_B[1:0] = ram_rdata_b[1:0]; - endcase - MODE_1: RDATA_B[0] = ram_rdata_b[ram_addr_b[3:0]]; - endcase -endmodule
diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_map.v b/ql-qlf-plugin/qlf_k6n10f/brams_map.v index 798ebbe..821cc44 100644 --- a/ql-qlf-plugin/qlf_k6n10f/brams_map.v +++ b/ql-qlf-plugin/qlf_k6n10f/brams_map.v
@@ -14,12 +14,12 @@ // // SPDX-License-Identifier: Apache-2.0 -`define MODE_36 3'b111 // 36 or 32-bit -`define MODE_18 3'b110 // 18 or 16-bit -`define MODE_9 3'b101 // 9 or 8-bit +`define MODE_36 3'b011 // 36 or 32-bit +`define MODE_18 3'b010 // 18 or 16-bit +`define MODE_9 3'b001 // 9 or 8-bit `define MODE_4 3'b100 // 4-bit -`define MODE_2 3'b010 // 32-bit -`define MODE_1 3'b001 // 32-bit +`define MODE_2 3'b110 // 32-bit +`define MODE_1 3'b101 // 32-bit module \$__QLF_FACTOR_BRAM36_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN); parameter CFG_ABITS = 10; @@ -53,22 +53,6 @@ wire FLUSH1; wire FLUSH2; wire SPLIT; - wire [15:0] RAM_ID; - - wire PL_INIT_i; - wire PL_ENA_i; - wire PL_REN_i; - wire PL_CLK_i; - wire [1:0] PL_WEN_i; - wire [23:0] PL_ADDR_i; - wire [35:0] PL_DATA_i; - reg PL_INIT_o; - reg PL_ENA_o; - reg PL_REN_o; - reg PL_CLK_o; - reg [1:0] PL_WEN_o; - reg [23:0] PL_ADDR_o; - wire [35:0] PL_DATA_o; wire [14:CFG_ABITS] A1ADDR_CMPL = {15-CFG_ABITS{1'b0}}; wire [14:CFG_ABITS] B1ADDR_CMPL = {15-CFG_ABITS{1'b0}}; @@ -157,17 +141,9 @@ assign SPLIT = 1'b0; assign FLUSH1 = 1'b0; assign FLUSH2 = 1'b0; - assign RAM_ID = 16'b0; - assign PL_INIT_i = 1'b0; - assign PL_ENA_i = 1'b0; - assign PL_REN_i = 1'b0; - assign PL_CLK_i = 1'b0; - assign PL_WEN_i = 2'b0; - assign PL_ADDR_i = 24'b0; - assign PL_DATA_i = 36'b0; - - TDP_BRAM36 _TECHMAP_REPLACE_ ( + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), .WDATA_A1_i(B1DATA[17:0]), .WDATA_A2_i(B1DATA[35:18]), .RDATA_A1_o(A1DATA_TOTAL[17:0]), @@ -199,24 +175,7 @@ .BE_B2_i({D1EN[3],D1EN[2]}), .FLUSH1_i(FLUSH1), - .FLUSH2_i(FLUSH2), - .RAM_ID_i(RAM_ID), - - .PL_INIT_i(PL_INIT_i), - .PL_ENA_i(PL_ENA_i), - .PL_WEN_i(PL_WEN_i), - .PL_REN_i(PL_REN_i), - .PL_CLK_i(PL_CLK_i), - .PL_ADDR_i(PL_ADDR_i), - .PL_DATA_i(PL_DATA_i), - .PL_INIT_o(PL_INIT_o), - .PL_ENA_o(PL_ENA_o), - .PL_WEN_o(PL_WEN_o), - .PL_REN_o(PL_REN_o), - .PL_CLK_o(PL_CLK_o), - .PL_ADDR_o(), - .PL_DATA_o(PL_DATA_o) - + .FLUSH2_i(FLUSH2) ); endmodule @@ -383,22 +342,6 @@ wire FLUSH1; wire FLUSH2; - wire [15:0] RAM_ID; - - wire PL_INIT_i; - wire PL_ENA_i; - wire PL_REN_i; - wire PL_CLK_i; - wire [1:0] PL_WEN_i; - wire [23:0] PL_ADDR_i; - wire [35:0] PL_DATA_i; - reg PL_INIT_o; - reg PL_ENA_o; - reg PL_REN_o; - reg PL_CLK_o; - reg [1:0] PL_WEN_o; - reg [23:0] PL_ADDR_o; - wire [35:0] PL_DATA_o; assign A1ADDR_CMPL = {15-CFG_ABITS{1'b0}}; assign B1ADDR_CMPL = {15-CFG_ABITS{1'b0}}; @@ -474,16 +417,9 @@ assign FLUSH1 = 1'b0; assign FLUSH2 = 1'b0; - assign RAM_ID = 16'b0; - assign PL_INIT_i = 1'b0; - assign PL_ENA_i = 1'b0; - assign PL_REN_i = 1'b0; - assign PL_CLK_i = 1'b0; - assign PL_WEN_i = 2'b0; - assign PL_ADDR_i = 24'b0; - assign PL_DATA_i = 36'b0; - TDP_BRAM36 _TECHMAP_REPLACE_ ( + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), .WDATA_A1_i(18'h3FFFF), .WDATA_A2_i(18'h3FFFF), .RDATA_A1_o(A1DATA_TOTAL[17:0]), @@ -515,24 +451,7 @@ .BE_B2_i(B1EN[3:2]), .FLUSH1_i(FLUSH1), - .FLUSH2_i(FLUSH2), - .RAM_ID_i(RAM_ID), - - .PL_INIT_i(PL_INIT_i), - .PL_ENA_i(PL_ENA_i), - .PL_WEN_i(PL_WEN_i), - .PL_REN_i(PL_REN_i), - .PL_CLK_i(PL_CLK_i), - .PL_ADDR_i(PL_ADDR_i), - .PL_DATA_i(PL_DATA_i), - .PL_INIT_o(PL_INIT_o), - .PL_ENA_o(PL_ENA_o), - .PL_WEN_o(PL_WEN_o), - .PL_REN_o(PL_REN_o), - .PL_CLK_o(PL_CLK_o), - .PL_ADDR_o(), - .PL_DATA_o(PL_DATA_o) - + .FLUSH2_i(FLUSH2) ); endmodule
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v index bf1648f..c9c881e 100644 --- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v +++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -495,7 +495,9 @@ endmodule -module TDP_BRAM36 ( +`default_nettype wire +module TDP36K ( + RESET_ni, WEN_A1_i, WEN_B1_i, REN_A1_i, @@ -525,22 +527,7 @@ WDATA_B2_i, RDATA_A2_o, RDATA_B2_o, - FLUSH2_i, - RAM_ID_i, - PL_INIT_i, - PL_ENA_i, - PL_REN_i, - PL_CLK_i, - PL_WEN_i, - PL_ADDR_i, - PL_DATA_i, - PL_INIT_o, - PL_ENA_o, - PL_REN_o, - PL_CLK_o, - PL_WEN_o, - PL_ADDR_o, - PL_DATA_o + FLUSH2_i ); parameter [80:0] MODE_BITS = 81'd0; @@ -559,10 +546,10 @@ // Second 18K RAMFIFO (39 bits) localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; - localparam [ 0:0] RMODE_A2_i = MODE_BITS[44:42]; - localparam [ 0:0] RMODE_B2_i = MODE_BITS[47:45]; - localparam [ 0:0] WMODE_A2_i = MODE_BITS[50:48]; - localparam [ 0:0] WMODE_B2_i = MODE_BITS[53:51]; + localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; + localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; + localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; + localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; localparam [ 0:0] FMODE2_i = MODE_BITS[54]; localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; @@ -718,6 +705,7 @@ parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + input RESET_ni; input wire WEN_A1_i; input wire WEN_B1_i; input wire REN_A1_i; @@ -752,21 +740,6 @@ output reg [17:0] RDATA_A2_o; output reg [17:0] RDATA_B2_o; input wire FLUSH2_i; - input wire [15:0] RAM_ID_i; - input wire PL_INIT_i; - input wire PL_ENA_i; - input wire PL_REN_i; - input wire PL_CLK_i; - input wire [1:0] PL_WEN_i; - input wire [31:0] PL_ADDR_i; - input wire [35:0] PL_DATA_i; - output reg PL_INIT_o; - output reg PL_ENA_o; - output reg PL_REN_o; - output reg PL_CLK_o; - output reg [1:0] PL_WEN_o; - output reg [31:0] PL_ADDR_o; - output reg [35:0] PL_DATA_o; wire EMPTY2; wire EPO2; wire EWM2; @@ -815,14 +788,14 @@ reg [1:0] ram_be_a2; reg [1:0] ram_be_b1; reg [1:0] ram_be_b2; - reg [2:0] ram_rmode_a1; - reg [2:0] ram_wmode_a1; - reg [2:0] ram_rmode_b1; - reg [2:0] ram_wmode_b1; - reg [2:0] ram_rmode_a2; - reg [2:0] ram_wmode_a2; - reg [2:0] ram_rmode_b2; - reg [2:0] ram_wmode_b2; + wire [2:0] ram_rmode_a1; + wire [2:0] ram_wmode_a1; + wire [2:0] ram_rmode_b1; + wire [2:0] ram_wmode_b1; + wire [2:0] ram_rmode_a2; + wire [2:0] ram_wmode_a2; + wire [2:0] ram_rmode_b2; + wire [2:0] ram_wmode_b2; wire ram_ren_a1; wire ram_ren_b1; wire ram_ren_a2; @@ -835,22 +808,36 @@ wire [11:0] ff_raddr; wire [11:0] ff_waddr; reg [35:0] fifo_rdata; - reg [1:0] fifo_rmode; - reg [1:0] fifo_wmode; + wire [1:0] fifo_rmode; + wire [1:0] fifo_wmode; wire [1:0] bwl; wire [17:0] pl_dout0; wire [17:0] pl_dout1; + wire sclk_a1; + wire sclk_b1; + wire sclk_a2; + wire sclk_b2; + wire sreset; + wire flush1; + wire flush2; + assign sreset = RESET_ni; + assign flush1 = ~FLUSH1_i; + assign flush2 = ~FLUSH2_i; assign ram_fmode1 = FMODE1_i & SPLIT_i; assign ram_fmode2 = FMODE2_i & SPLIT_i; assign smux_clk_a1 = CLK_A1_i; assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); - assign smux_clk_b2 = (SPLIT_i ? CLK_B2_i : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign sclk_a1 = smux_clk_a1; + assign sclk_a2 = smux_clk_a2; + assign sclk_b1 = smux_clk_b1; + assign sclk_b2 = smux_clk_b2; assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); - localparam MODE_36 = 3'b111; + localparam MODE_36 = 3'b011; assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); @@ -860,8 +847,8 @@ assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); - localparam MODE_18 = 3'b110; - localparam MODE_9 = 3'b101; + localparam MODE_18 = 3'b010; + localparam MODE_9 = 3'b001; always @(*) begin : WDATA_SEL case (SPLIT_i) 1: begin @@ -877,8 +864,8 @@ 0: begin case (WMODE_A1_i) MODE_36: begin - ram_wdata_a1 = {WDATA_A2_i[15:14], WDATA_A1_i[15:0]}; - ram_wdata_a2 = {WDATA_A2_i[17:16], WDATA_A2_i[13:0], WDATA_A1_i[17:16]}; + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); end @@ -888,40 +875,22 @@ ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); end - MODE_9: + MODE_9: begin + ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a1[16] = WDATA_A1_i[16]; + ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a1[17] = WDATA_A1_i[16]; + ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a2[16] = WDATA_A1_i[16]; + ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a2[17] = WDATA_A1_i[16]; case (bwl) - 0: begin - ram_wdata_a1[8:0] = (FMODE1_i ? {WDATA_A1_i[0], WDATA_A1_i[7:0]} : WDATA_A1_i[8:0]); - ram_wdata_a1[17:9] = (FMODE1_i ? {{2 {WDATA_A1_i[8]}}, WDATA_A1_i[7:1]} : 9'b000000000); - ram_wdata_a2[8:0] = (FMODE1_i ? {WDATA_A1_i[0], WDATA_A1_i[7:0]} : 9'b000000000); - ram_wdata_a2[17:9] = (FMODE1_i ? {{2 {WDATA_A1_i[8]}}, WDATA_A1_i[7:1]} : 9'b000000000); - ram_be_a1[0] = (FMODE1_i ? (ff_waddr[1:0] == 0 ? 1'b1 : 1'b0) : 1'b1); - ram_be_a1[1] = (FMODE1_i ? (ff_waddr[1:0] == 1 ? 1'b1 : 1'b0) : 1'b0); - ram_be_a2[0] = (FMODE1_i ? (ff_waddr[1:0] == 2 ? 1'b1 : 1'b0) : 1'b0); - ram_be_a2[1] = (FMODE1_i ? (ff_waddr[1:0] == 3 ? 1'b1 : 1'b0) : 1'b0); - end - 1: begin - ram_wdata_a1[8:0] = (FMODE1_i ? {WDATA_A1_i[0], WDATA_A1_i[7:0]} : WDATA_A1_i[8:0]); - ram_wdata_a1[17:9] = (FMODE1_i ? {{2 {WDATA_A1_i[8]}}, WDATA_A1_i[7:1]} : 9'b000000000); - ram_wdata_a2[8:0] = (FMODE1_i ? {WDATA_A1_i[0], WDATA_A1_i[7:0]} : 9'b000000000); - ram_wdata_a2[17:9] = (FMODE1_i ? {{2 {WDATA_A1_i[8]}}, WDATA_A1_i[7:1]} : 9'b000000000); - {ram_be_a2, ram_be_a1} = 4'b0010; - end - 2: begin - ram_wdata_a1[8:0] = (FMODE1_i ? {WDATA_A1_i[0], WDATA_A1_i[7:0]} : 9'b000000000); - ram_wdata_a1[17:9] = (FMODE1_i ? {{2 {WDATA_A1_i[8]}}, WDATA_A1_i[7:1]} : 9'b000000000); - ram_wdata_a2[8:0] = (FMODE1_i ? {WDATA_A1_i[0], WDATA_A1_i[7:0]} : WDATA_A1_i[8:0]); - ram_wdata_a2[17:9] = (FMODE1_i ? {{2 {WDATA_A1_i[8]}}, WDATA_A1_i[7:1]} : 9'b000000000); - {ram_be_a2, ram_be_a1} = 4'b0100; - end - 3: begin - ram_wdata_a1[8:0] = (FMODE1_i ? {WDATA_A1_i[0], WDATA_A1_i[7:0]} : 9'b000000000); - ram_wdata_a1[17:9] = (FMODE1_i ? {{2 {WDATA_A1_i[8]}}, WDATA_A1_i[7:1]} : 9'b000000000); - ram_wdata_a2[8:0] = (FMODE1_i ? {WDATA_A1_i[0], WDATA_A1_i[7:0]} : WDATA_A1_i[8:0]); - ram_wdata_a2[17:9] = (FMODE1_i ? {{2 {WDATA_A1_i[8]}}, WDATA_A1_i[7:1]} : 9'b000000000); - {ram_be_a2, ram_be_a1} = 4'b1000; - end + 0: {ram_be_a2, ram_be_a1} = 4'b0001; + 1: {ram_be_a2, ram_be_a1} = 4'b0010; + 2: {ram_be_a2, ram_be_a1} = 4'b0100; + 3: {ram_be_a2, ram_be_a1} = 4'b1000; endcase + end default: begin ram_wdata_a1 = WDATA_A1_i; ram_wdata_a2 = WDATA_A1_i; @@ -931,8 +900,8 @@ endcase case (WMODE_B1_i) MODE_36: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : {WDATA_B2_i[15:14], WDATA_B1_i[15:0]}); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : {WDATA_B2_i[17:16], WDATA_B2_i[13:0], WDATA_B1_i[17:16]}); + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); ram_be_b2 = BE_B2_i; ram_be_b1 = BE_B1_i; end @@ -942,37 +911,22 @@ ram_be_b1 = BE_B1_i; ram_be_b2 = BE_B1_i; end - MODE_9: + MODE_9: begin + ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b1[16] = WDATA_B1_i[16]; + ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b1[17] = WDATA_B1_i[16]; + ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b2[16] = WDATA_B1_i[16]; + ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b2[17] = WDATA_B1_i[16]; case (ADDR_B1_i[4:3]) - 0: begin - ram_wdata_b1[8:0] = WDATA_B1_i[8:0]; - ram_wdata_b1[17:9] = 9'b000000000; - ram_wdata_b2[8:0] = 9'b000000000; - ram_wdata_b2[17:9] = 9'b000000000; - {ram_be_b2, ram_be_b1} = 4'b0001; - end - 1: begin - ram_wdata_b1[8:0] = WDATA_B1_i[8:0]; - ram_wdata_b1[17:9] = 9'b000000000; - ram_wdata_b2[8:0] = 9'b000000000; - ram_wdata_b2[17:9] = 9'b000000000; - {ram_be_b2, ram_be_b1} = 4'b0010; - end - 2: begin - ram_wdata_b1[8:0] = 9'b000000000; - ram_wdata_b1[17:9] = 9'b000000000; - ram_wdata_b2[8:0] = WDATA_B1_i[8:0]; - ram_wdata_b2[17:9] = 9'b000000000; - {ram_be_b2, ram_be_b1} = 4'b0100; - end - 3: begin - ram_wdata_b1[8:0] = 9'b000000000; - ram_wdata_b1[17:9] = 9'b000000000; - ram_wdata_b2[8:0] = WDATA_B1_i[8:0]; - ram_wdata_b2[17:9] = 9'b000000000; - {ram_be_b2, ram_be_b1} = 4'b1000; - end + 0: {ram_be_b2, ram_be_b1} = 4'b0001; + 1: {ram_be_b2, ram_be_b1} = 4'b0010; + 2: {ram_be_b2, ram_be_b1} = 4'b0100; + 3: {ram_be_b2, ram_be_b1} = 4'b1000; endcase + end default: begin ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); @@ -983,43 +937,30 @@ end endcase end - always @(posedge CLK_A1_i or posedge CLK_B1_i or posedge CLK_A2_i or posedge CLK_B2_i) begin - if (!SPLIT_i) begin - ram_rmode_a1 <= (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i); - ram_rmode_a2 <= (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i); - ram_wmode_a1 <= (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i)); - ram_wmode_a2 <= (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i)); - ram_rmode_b1 <= (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i)); - ram_rmode_b2 <= (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i)); - ram_wmode_b1 <= (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i); - ram_wmode_b2 <= (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i); - end else begin - ram_rmode_a1 <= (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i); - ram_rmode_a2 <= (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i); - ram_wmode_a1 <= (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i); - ram_wmode_a2 <= (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i); - ram_rmode_b1 <= (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i); - ram_rmode_b2 <= (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i); - ram_wmode_b1 <= (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i); - ram_wmode_b2 <= (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i); - end - end + assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); always @(*) begin : FIFO_READ_SEL case (RMODE_B1_i) MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); MODE_9: case (ff_raddr[1:0]) - 0: fifo_rdata = {27'b000000000000000000000000000, ram_rdata_b1[16], ram_rdata_b1[7:0]}; - 1: fifo_rdata = {27'b000000000000000000000000000, ram_rdata_b1[17], ram_rdata_b1[15:8]}; - 2: fifo_rdata = {27'b000000000000000000000000000, ram_rdata_b2[16], ram_rdata_b2[7:0]}; - 3: fifo_rdata = {27'b000000000000000000000000000, ram_rdata_b2[17], ram_rdata_b2[15:8]}; + 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; + 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; + 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; + 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; endcase - default: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; + default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; endcase end - localparam MODE_1 = 3'b001; - localparam MODE_2 = 3'b010; + localparam MODE_1 = 3'b101; + localparam MODE_2 = 3'b110; localparam MODE_4 = 3'b100; always @(*) begin : RDATA_SEL case (SPLIT_i) @@ -1037,15 +978,15 @@ else case (RMODE_A1_i) MODE_36: begin - RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; - RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; + RDATA_A1_o = {ram_rdata_a1[17:0]}; + RDATA_A2_o = {ram_rdata_a2[17:0]}; end MODE_18: begin RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); RDATA_A2_o = 18'b000000000000000000; end MODE_9: begin - RDATA_A1_o = (laddr_a1[4] ? {9'b000000000, ram_rdata_a2[8:0]} : {9'b000000000, ram_rdata_a1[8:0]}); + RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); RDATA_A2_o = 18'b000000000000000000; end MODE_4: begin @@ -1070,15 +1011,15 @@ endcase case (RMODE_B1_i) MODE_36: begin - RDATA_B1_o = {ram_rdata_b2[1:0], ram_rdata_b1[15:0]}; - RDATA_B2_o = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:2]}; + RDATA_B1_o = {ram_rdata_b1}; + RDATA_B2_o = {ram_rdata_b2}; end MODE_18: begin RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); RDATA_B2_o = 18'b000000000000000000; end MODE_9: begin - RDATA_B1_o = (FMODE1_i ? {9'b000000000, fifo_rdata[8:0]} : (laddr_b1[4] ? {9'b000000000, ram_rdata_b2[8:0]} : {9'b000000000, ram_rdata_b1[8:0]})); + RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); RDATA_B2_o = 18'b000000000000000000; end MODE_4: begin @@ -1097,46 +1038,37 @@ RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); end default: begin - RDATA_B1_o = {ram_rdata_b2[1:0], ram_rdata_b1[15:0]}; - RDATA_B2_o = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:2]}; + RDATA_B1_o = ram_rdata_b1; + RDATA_B2_o = ram_rdata_b2; end endcase end endcase end - always @(posedge CLK_A1_i) laddr_a1 <= ADDR_A1_i; - always @(posedge CLK_B1_i) laddr_b1 <= ADDR_B1_i; - always @(posedge CLK_A1_i or posedge CLK_B1_i or posedge CLK_A2_i or posedge CLK_B2_i) begin - if (WMODE_A1_i == MODE_36) - fifo_wmode = 2'b00; - else if (WMODE_A1_i == MODE_18) - fifo_wmode = 2'b01; - else if (WMODE_A1_i == MODE_9) - fifo_wmode = 2'b10; + always @(posedge sclk_a1 or negedge sreset) + if (sreset == 0) + laddr_a1 <= 1'sb0; else - fifo_wmode = 2'b00; - - if (RMODE_B1_i == MODE_36) - fifo_rmode = 2'b00; - else if (RMODE_B1_i == MODE_18) - fifo_rmode = 2'b01; - else if (RMODE_B1_i == MODE_9) - fifo_rmode = 2'b10; + laddr_a1 <= ADDR_A1_i; + always @(posedge sclk_b1 or negedge sreset) + if (sreset == 0) + laddr_b1 <= 1'sb0; else - fifo_rmode = 2'b00; - end + laddr_b1 <= ADDR_B1_i; + assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); + assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); fifo_ctl #( .ADDR_WIDTH(12), - .FIFO_WIDTH(3'd4) + .FIFO_WIDTH(3'd4), + .DEPTH(7) ) fifo36_ctl( - .rclk(smux_clk_b1), - .rst_R_n(~FLUSH1_i), - .wclk(smux_clk_a1), - .rst_W_n(~FLUSH1_i), + .rclk(sclk_b1), + .rst_R_n(flush1), + .wclk(sclk_a1), + .rst_W_n(flush1), .ren(REN_B1_i), .wen(ram_wen_a1), .sync(SYNC_FIFO1_i), - .depth(3'b111), .rmode(fifo_rmode), .wmode(fifo_wmode), .ren_o(ren_o), @@ -1147,110 +1079,81 @@ .upae(UPAE1_i) ); TDP18K_FIFO #( - .UPAF(UPAF1_i[10:0]), - .UPAE(UPAE1_i[10:0]), - .SYNC_FIFO(SYNC_FIFO1_i), - .POWERDN(POWERDN1_i), - .SLEEP(SLEEP1_i), - .PROTECT(PROTECT1_i) + .UPAF_i(UPAF1_i[10:0]), + .UPAE_i(UPAE1_i[10:0]), + .SYNC_FIFO_i(SYNC_FIFO1_i), + .POWERDN_i(POWERDN1_i), + .SLEEP_i(SLEEP1_i), + .PROTECT_i(PROTECT1_i) )u1( - .RMODE_A(ram_rmode_a1), - .RMODE_B(ram_rmode_b1), - .WMODE_A(ram_wmode_a1), - .WMODE_B(ram_wmode_b1), - .WEN_A(ram_wen_a1), - .WEN_B(ram_wen_b1), - .REN_A(ram_ren_a1), - .REN_B(ram_ren_b1), - .CLK_A(smux_clk_a1), - .CLK_B(smux_clk_b1), - .BE_A(ram_be_a1), - .BE_B(ram_be_b1), - .ADDR_A(ram_addr_a1), - .ADDR_B(ram_addr_b1), - .WDATA_A(ram_wdata_a1), - .WDATA_B(ram_wdata_b1), - .RDATA_A(ram_rdata_a1), - .RDATA_B(ram_rdata_b1), - .EMPTY(EMPTY1), - .EPO(EPO1), - .EWM(EWM1), - .UNDERRUN(UNDERRUN1), - .FULL(FULL1), - .FMO(FMO1), - .FWM(FWM1), - .OVERRUN(OVERRUN1), - .FLUSH(FLUSH1_i), - .RAM_ID({RAM_ID_i}), - .FMODE(ram_fmode1), - .PL_INIT(PL_INIT_i), - .PL_ENA(PL_ENA_i), - .PL_WEN(PL_WEN_i[0]), - .PL_REN(PL_REN_i), - .PL_CLK(PL_CLK_i), - .PL_ADDR(PL_ADDR_i), - .PL_DATA_IN({PL_DATA_i[33:32], PL_DATA_i[15:0]}), - .PL_DATA_OUT(pl_dout0) + .RMODE_A_i(ram_rmode_a1), + .RMODE_B_i(ram_rmode_b1), + .WMODE_A_i(ram_wmode_a1), + .WMODE_B_i(ram_wmode_b1), + .WEN_A_i(ram_wen_a1), + .WEN_B_i(ram_wen_b1), + .REN_A_i(ram_ren_a1), + .REN_B_i(ram_ren_b1), + .CLK_A_i(sclk_a1), + .CLK_B_i(sclk_b1), + .BE_A_i(ram_be_a1), + .BE_B_i(ram_be_b1), + .ADDR_A_i(ram_addr_a1), + .ADDR_B_i(ram_addr_b1), + .WDATA_A_i(ram_wdata_a1), + .WDATA_B_i(ram_wdata_b1), + .RDATA_A_o(ram_rdata_a1), + .RDATA_B_o(ram_rdata_b1), + .EMPTY_o(EMPTY1), + .EPO_o(EPO1), + .EWM_o(EWM1), + .UNDERRUN_o(UNDERRUN1), + .FULL_o(FULL1), + .FMO_o(FMO1), + .FWM_o(FWM1), + .OVERRUN_o(OVERRUN1), + .FLUSH_ni(flush1), + .FMODE_i(ram_fmode1) ); TDP18K_FIFO #( - .UPAF(UPAF2_i[10:0]), - .UPAE(UPAE2_i[10:0]), - .SYNC_FIFO(SYNC_FIFO2_i), - .POWERDN(POWERDN2_i), - .SLEEP(SLEEP2_i), - .PROTECT(PROTECT2_i) + .UPAF_i(UPAF2_i), + .UPAE_i(UPAE2_i), + .SYNC_FIFO_i(SYNC_FIFO2_i), + .POWERDN_i(POWERDN2_i), + .SLEEP_i(SLEEP2_i), + .PROTECT_i(PROTECT2_i) )u2( - .RMODE_A(ram_rmode_a2), - .RMODE_B(ram_rmode_b2), - .WMODE_A(ram_wmode_a2), - .WMODE_B(ram_wmode_b2), - .WEN_A(ram_wen_a2), - .WEN_B(ram_wen_b2), - .REN_A(ram_ren_a2), - .REN_B(ram_ren_b2), - .CLK_A(smux_clk_a2), - .CLK_B(smux_clk_b2), - .BE_A(ram_be_a2), - .BE_B(ram_be_b2), - .ADDR_A(ram_addr_a2), - .ADDR_B(ram_addr_b2), - .WDATA_A(ram_wdata_a2), - .WDATA_B(ram_wdata_b2), - .RDATA_A(ram_rdata_a2), - .RDATA_B(ram_rdata_b2), - .EMPTY(EMPTY2), - .EPO(EPO2), - .EWM(EWM2), - .UNDERRUN(UNDERRUN2), - .FULL(FULL2), - .FMO(FMO2), - .FWM(FWM2), - .OVERRUN(OVERRUN2), - .FLUSH(FLUSH2_i), - .RAM_ID({RAM_ID_i}), - .FMODE(ram_fmode2), - .PL_INIT(PL_INIT_i), - .PL_ENA(PL_ENA_i), - .PL_WEN(PL_WEN_i[1]), - .PL_REN(PL_REN_i), - .PL_CLK(PL_CLK_i), - .PL_ADDR(PL_ADDR_i), - .PL_DATA_IN({PL_DATA_i[35:34], PL_DATA_i[31:16]}), - .PL_DATA_OUT(pl_dout1) + .RMODE_A_i(ram_rmode_a2), + .RMODE_B_i(ram_rmode_b2), + .WMODE_A_i(ram_wmode_a2), + .WMODE_B_i(ram_wmode_b2), + .WEN_A_i(ram_wen_a2), + .WEN_B_i(ram_wen_b2), + .REN_A_i(ram_ren_a2), + .REN_B_i(ram_ren_b2), + .CLK_A_i(sclk_a2), + .CLK_B_i(sclk_b2), + .BE_A_i(ram_be_a2), + .BE_B_i(ram_be_b2), + .ADDR_A_i(ram_addr_a2), + .ADDR_B_i(ram_addr_b2), + .WDATA_A_i(ram_wdata_a2), + .WDATA_B_i(ram_wdata_b2), + .RDATA_A_o(ram_rdata_a2), + .RDATA_B_o(ram_rdata_b2), + .EMPTY_o(EMPTY2), + .EPO_o(EPO2), + .EWM_o(EWM2), + .UNDERRUN_o(UNDERRUN2), + .FULL_o(FULL2), + .FMO_o(FMO2), + .FWM_o(FWM2), + .OVERRUN_o(OVERRUN2), + .FLUSH_ni(flush2), + .FMODE_i(ram_fmode2) ); - always @(*) begin - if (RAM_ID_i == PL_ADDR_i[31:16]) - PL_DATA_o = (PL_REN_i ? {pl_dout1[17:16], pl_dout0[17:16], pl_dout1[15:0], pl_dout0[15:0]} : PL_DATA_i); - else - PL_DATA_o = PL_DATA_i; - PL_ADDR_o = PL_ADDR_i; - PL_INIT_o = PL_INIT_i; - PL_ENA_o = PL_ENA_i; - PL_WEN_o = PL_WEN_i; - PL_REN_o = PL_REN_i; - PL_CLK_o = PL_CLK_i; - end endmodule +`default_nettype none (* blackbox *) module QL_DSP1 (
diff --git a/ql-qlf-plugin/qlf_k6n10f/sram1024x18.v b/ql-qlf-plugin/qlf_k6n10f/sram1024x18.v index 60cd586..864b886 100644 --- a/ql-qlf-plugin/qlf_k6n10f/sram1024x18.v +++ b/ql-qlf-plugin/qlf_k6n10f/sram1024x18.v
@@ -14,6 +14,7 @@ // // SPDX-License-Identifier: Apache-2.0 +`default_nettype wire module sram1024x18 ( clk_a, cen_a, @@ -130,3 +131,4 @@ rdata_a = rdata_a; end endmodule +`default_nettype none
diff --git a/ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v b/ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v index 0c1dcc0..441f6bc 100644 --- a/ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v +++ b/ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v
@@ -14,13 +14,13 @@ // // SPDX-License-Identifier: Apache-2.0 +`default_nettype wire module fifo_ctl ( raddr, waddr, fflags, ren_o, sync, - depth, rmode, wmode, rclk, @@ -34,13 +34,12 @@ ); parameter ADDR_WIDTH = 11; parameter FIFO_WIDTH = 3'd2; - localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + parameter DEPTH = 6; output wire [ADDR_WIDTH - 1:0] raddr; output wire [ADDR_WIDTH - 1:0] waddr; output wire [7:0] fflags; output wire ren_o; input wire sync; - input wire [2:0] depth; input wire [1:0] rmode; input wire [1:0] wmode; (* clkbuf_sink *) @@ -53,6 +52,7 @@ input wire wen; input wire [ADDR_WIDTH - 1:0] upaf; input wire [ADDR_WIDTH - 1:0] upae; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; reg [ADDR_WIDTH:0] pushtopop1; reg [ADDR_WIDTH:0] pushtopop2; reg [ADDR_WIDTH:0] poptopush1; @@ -65,23 +65,26 @@ assign smux_pushtopop = (sync ? pushtopop0 : pushtopop2); always @(posedge rclk or negedge rst_R_n) if (~rst_R_n) begin - pushtopop1 <= #(1) {ADDR_WIDTH + 1{1'h0}}; - pushtopop2 <= #(1) {ADDR_WIDTH + 1{1'h0}}; + pushtopop1 <= 'h0; + pushtopop2 <= 'h0; end else begin - pushtopop1 <= #(1) pushtopop0; - pushtopop2 <= #(1) pushtopop1; + pushtopop1 = pushtopop0; + pushtopop2 = pushtopop1; end always @(posedge wclk or negedge rst_W_n) if (~rst_W_n) begin - poptopush1 <= #(1) {ADDR_WIDTH + 1{1'h0}}; - poptopush2 <= #(1) {ADDR_WIDTH + 1{1'h0}}; + poptopush1 <= 'h0; + poptopush2 <= 'h0; end else begin - poptopush1 <= #(1) poptopush0; - poptopush2 <= #(1) poptopush1; + poptopush1 <= poptopush0; + poptopush2 <= poptopush1; end - fifo_push #(.ADDR_WIDTH(ADDR_WIDTH)) u_fifo_push( + fifo_push #( + .ADDR_WIDTH(ADDR_WIDTH), + .DEPTH(DEPTH) + ) u_fifo_push( .wclk(wclk), .wen(wen), .rst_n(rst_W_n), @@ -90,13 +93,13 @@ .gcout(pushtopop0), .gcin(smux_poptopush), .ff_waddr(waddr), - .depth(depth), .pushflags(fflags[7:4]), .upaf(upaf) ); fifo_pop #( .ADDR_WIDTH(ADDR_WIDTH), - .FIFO_WIDTH(FIFO_WIDTH) + .FIFO_WIDTH(FIFO_WIDTH), + .DEPTH(DEPTH) ) u_fifo_pop( .rclk(rclk), .ren_in(ren), @@ -107,7 +110,6 @@ .gcout(poptopush0), .gcin(smux_pushtopop), .out_raddr(raddr), - .depth(depth), .popflags(fflags[3:0]), .upae(upae) ); @@ -121,22 +123,23 @@ wen, rmode, wmode, - depth, gcin, upaf ); parameter ADDR_WIDTH = 11; + parameter DEPTH = 6; output wire [3:0] pushflags; output wire [ADDR_WIDTH:0] gcout; output wire [ADDR_WIDTH - 1:0] ff_waddr; input rst_n; + (* clkbuf_sink *) input wclk; input wen; input [1:0] rmode; input [1:0] wmode; - input [2:0] depth; input [ADDR_WIDTH:0] gcin; input [ADDR_WIDTH - 1:0] upaf; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; reg full_next; reg full; reg paf_next; @@ -165,22 +168,13 @@ wire [ADDR_WIDTH:0] tmp; wire [ADDR_WIDTH:0] next_count; wire [ADDR_WIDTH:0] count; - reg [ADDR_WIDTH:0] fbytes; + wire [ADDR_WIDTH:0] fbytes; genvar i; assign next_count = fbytes - (waddr_next >= raddr_next ? waddr_next - raddr_next : (~raddr_next + waddr_next) + 1); assign count = fbytes - (waddr >= raddr ? waddr - raddr : (~raddr + waddr) + 1); + assign fbytes = 1 << (DEPTH + 5); always @(*) begin - case (depth) - 3'b000: fbytes = {ADDR_WIDTH + 1{1'h0}} | 12'd2048; - 3'b001: fbytes = {ADDR_WIDTH + 1{1'h0}} | 11'd1024; - 3'b010: fbytes = {ADDR_WIDTH + 1{1'h0}} | 10'd512; - 3'b011: fbytes = {ADDR_WIDTH + 1{1'h0}} | 9'd256; - 3'b100: fbytes = {ADDR_WIDTH + 1{1'h0}} | 8'd128; - 3'b101: fbytes = {ADDR_WIDTH + 1{1'h0}} | 7'd64; - 3'b110: fbytes = {ADDR_WIDTH + 1{1'h0}} | 6'd32; - 3'b111: fbytes = {ADDR_WIDTH + 1{1'h0}} | 13'd4096; - endcase - paf_thresh = (wmode ? (wmode[0] ? upaf << 1 : upaf) : upaf << 2); + paf_thresh = wmode[1] ? upaf : (wmode[0] ? upaf << 1 : upaf << 2); end always @(*) case (wmode) @@ -200,24 +194,24 @@ f2 = 1'b0; p1 = 1'b0; p2 = 1'b0; - q1 = next_count < paf_thresh; - q2 = count < paf_thresh; + q1 = next_count < {1'b0, paf_thresh}; + q2 = count < {1'b0, paf_thresh}; case (wmode) 2'h0: - case (depth) - 3'h0: begin + case (DEPTH) + 3'h6: begin f1 = {~waddr_next[11], waddr_next[10:2]} == raddr_next[11:2]; f2 = {~waddr[11], waddr[10:2]} == raddr_next[11:2]; p1 = ((waddr_next[10:2] + 1) & 9'h1ff) == raddr_next[10:2]; p2 = ((waddr[10:2] + 1) & 9'h1ff) == raddr_next[10:2]; end - 3'h1: begin + 3'h5: begin f1 = {~waddr_next[10], waddr_next[9:2]} == raddr_next[10:2]; f2 = {~waddr[10], waddr[9:2]} == raddr_next[10:2]; p1 = ((waddr_next[9:2] + 1) & 8'hff) == raddr_next[9:2]; p2 = ((waddr[9:2] + 1) & 8'hff) == raddr_next[9:2]; end - 3'h2: begin + 3'h4: begin f1 = {~waddr_next[9], waddr_next[8:2]} == raddr_next[9:2]; f2 = {~waddr[9], waddr[8:2]} == raddr_next[9:2]; p1 = ((waddr_next[8:2] + 1) & 7'h7f) == raddr_next[8:2]; @@ -229,19 +223,19 @@ p1 = ((waddr_next[7:2] + 1) & 6'h3f) == raddr_next[7:2]; p2 = ((waddr[7:2] + 1) & 6'h3f) == raddr_next[7:2]; end - 3'h4: begin + 3'h2: begin f1 = {~waddr_next[7], waddr_next[6:2]} == raddr_next[7:2]; f2 = {~waddr[7], waddr[6:2]} == raddr_next[7:2]; p1 = ((waddr_next[6:2] + 1) & 5'h1f) == raddr_next[6:2]; p2 = ((waddr[6:2] + 1) & 5'h1f) == raddr_next[6:2]; end - 3'h5: begin + 3'h1: begin f1 = {~waddr_next[6], waddr_next[5:2]} == raddr_next[6:2]; f2 = {~waddr[6], waddr[5:2]} == raddr_next[6:2]; p1 = ((waddr_next[5:2] + 1) & 4'hf) == raddr_next[5:2]; p2 = ((waddr[5:2] + 1) & 4'hf) == raddr_next[5:2]; end - 3'h6: begin + 3'h0: begin f1 = {~waddr_next[5], waddr_next[4:2]} == raddr_next[5:2]; f2 = {~waddr[5], waddr[4:2]} == raddr_next[5:2]; p1 = ((waddr_next[4:2] + 1) & 3'h7) == raddr_next[4:2]; @@ -249,26 +243,26 @@ end 3'h7: begin f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2]; - f2 = {~waddr[ADDR_WIDTH], waddr[10:2]} == raddr_next[ADDR_WIDTH:2]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2]; p1 = ((waddr_next[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2]; p2 = ((waddr[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2]; end endcase 2'h1: - case (depth) - 3'h0: begin + case (DEPTH) + 3'h6: begin f1 = {~waddr_next[11], waddr_next[10:1]} == raddr_next[11:1]; f2 = {~waddr[11], waddr[10:1]} == raddr_next[11:1]; p1 = ((waddr_next[10:1] + 1) & 10'h3ff) == raddr_next[10:1]; p2 = ((waddr[10:1] + 1) & 10'h3ff) == raddr_next[10:1]; end - 3'h1: begin + 3'h5: begin f1 = {~waddr_next[10], waddr_next[9:1]} == raddr_next[10:1]; f2 = {~waddr[10], waddr[9:1]} == raddr_next[10:1]; p1 = ((waddr_next[9:1] + 1) & 9'h1ff) == raddr_next[9:1]; p2 = ((waddr[9:1] + 1) & 9'h1ff) == raddr_next[9:1]; end - 3'h2: begin + 3'h4: begin f1 = {~waddr_next[9], waddr_next[8:1]} == raddr_next[9:1]; f2 = {~waddr[9], waddr[8:1]} == raddr_next[9:1]; p1 = ((waddr_next[8:1] + 1) & 8'hff) == raddr_next[8:1]; @@ -280,19 +274,19 @@ p1 = ((waddr_next[7:1] + 1) & 7'h7f) == raddr_next[7:1]; p2 = ((waddr[7:1] + 1) & 7'h7f) == raddr_next[7:1]; end - 3'h4: begin + 3'h2: begin f1 = {~waddr_next[7], waddr_next[6:1]} == raddr_next[7:1]; f2 = {~waddr[7], waddr[6:1]} == raddr_next[7:1]; p1 = ((waddr_next[6:1] + 1) & 6'h3f) == raddr_next[6:1]; p2 = ((waddr[6:1] + 1) & 6'h3f) == raddr_next[6:1]; end - 3'h5: begin + 3'h1: begin f1 = {~waddr_next[6], waddr_next[5:1]} == raddr_next[6:1]; f2 = {~waddr[6], waddr[5:1]} == raddr_next[6:1]; p1 = ((waddr_next[5:1] + 1) & 5'h1f) == raddr_next[5:1]; p2 = ((waddr[5:1] + 1) & 5'h1f) == raddr_next[5:1]; end - 3'h6: begin + 3'h0: begin f1 = {~waddr_next[5], waddr_next[4:1]} == raddr_next[5:1]; f2 = {~waddr[5], waddr[4:1]} == raddr_next[5:1]; p1 = ((waddr_next[4:1] + 1) & 4'hf) == raddr_next[4:1]; @@ -300,26 +294,26 @@ end 3'h7: begin f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; - f2 = {~waddr[11], waddr[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; p1 = ((waddr_next[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1]; p2 = ((waddr[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1]; end endcase 2'h2: - case (depth) - 3'h0: begin + case (DEPTH) + 3'h6: begin f1 = {~waddr_next[11], waddr_next[10:0]} == raddr_next[11:0]; f2 = {~waddr[11], waddr[10:0]} == raddr_next[11:0]; p1 = ((waddr_next[10:0] + 1) & 11'h7ff) == raddr_next[10:0]; p2 = ((waddr[10:0] + 1) & 11'h7ff) == raddr_next[10:0]; end - 3'h1: begin + 3'h5: begin f1 = {~waddr_next[10], waddr_next[9:0]} == raddr_next[10:0]; f2 = {~waddr[10], waddr[9:0]} == raddr_next[10:0]; p1 = ((waddr_next[9:0] + 1) & 10'h3ff) == raddr_next[9:0]; p2 = ((waddr[9:0] + 1) & 10'h3ff) == raddr_next[9:0]; end - 3'h2: begin + 3'h4: begin f1 = {~waddr_next[9], waddr_next[8:0]} == raddr_next[9:0]; f2 = {~waddr[9], waddr[8:0]} == raddr_next[9:0]; p1 = ((waddr_next[8:0] + 1) & 9'h1ff) == raddr_next[8:0]; @@ -331,19 +325,19 @@ p1 = ((waddr_next[7:0] + 1) & 8'hff) == raddr_next[7:0]; p2 = ((waddr[7:0] + 1) & 8'hff) == raddr_next[7:0]; end - 3'h4: begin + 3'h2: begin f1 = {~waddr_next[7], waddr_next[6:0]} == raddr_next[7:0]; f2 = {~waddr[7], waddr[6:0]} == raddr_next[7:0]; p1 = ((waddr_next[6:0] + 1) & 7'h7f) == raddr_next[6:0]; p2 = ((waddr[6:0] + 1) & 7'h7f) == raddr_next[6:0]; end - 3'h5: begin + 3'h1: begin f1 = {~waddr_next[6], waddr_next[5:0]} == raddr_next[6:0]; f2 = {~waddr[6], waddr[5:0]} == raddr_next[6:0]; p1 = ((waddr_next[5:0] + 1) & 6'h3f) == raddr_next[5:0]; p2 = ((waddr[5:0] + 1) & 6'h3f) == raddr_next[5:0]; end - 3'h6: begin + 3'h0: begin f1 = {~waddr_next[5], waddr_next[4:0]} == raddr_next[5:0]; f2 = {~waddr[5], waddr[4:0]} == raddr_next[5:0]; p1 = ((waddr_next[4:0] + 1) & 5'h1f) == raddr_next[4:0]; @@ -380,42 +374,42 @@ 2'h2: gcout_next = gc8out_next; 2'h1: gcout_next = {1'b0, gc16out_next}; 2'h0: gcout_next = {2'b00, gc32out_next}; - default: gcout_next = 12'h000; + default: gcout_next = {ADDR_PLUS_ONE {1'b0}}; endcase else - gcout_next = 12'h000; + gcout_next = {ADDR_PLUS_ONE {1'b0}}; always @(posedge wclk or negedge rst_n) if (~rst_n) begin - full <= #(1) 1'b0; - fmo <= #(1) 1'b0; - paf <= #(1) 1'b0; - raddr <= #(1) ADDR_WIDTH + 1'h0; + full <= 1'b0; + fmo <= 1'b0; + paf <= 1'b0; + raddr <= {ADDR_PLUS_ONE {1'b0}}; end else begin - full <= #(1) full_next; - fmo <= #(1) fmo_next; - paf <= #(1) paf_next; + full <= full_next; + fmo <= fmo_next; + paf <= paf_next; case (gmode) - 0: raddr <= #(1) raddr_next & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; - 1: raddr <= #(1) raddr_next & {{ADDR_WIDTH {1'b1}}, 1'b0}; - 2: raddr <= #(1) raddr_next & {ADDR_WIDTH + 1 {1'b1}}; - 3: raddr <= #(1) 12'h000; + 0: raddr <= raddr_next & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 1: raddr <= raddr_next & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2: raddr <= raddr_next & {ADDR_WIDTH + 1 {1'b1}}; + 3: raddr <= 12'h000; endcase end assign overflow_next = full & wen; always @(posedge wclk or negedge rst_n) if (~rst_n) - overflow <= #(1) 1'b0; + overflow <= 1'b0; else if (wen == 1'b1) - overflow <= #(1) overflow_next; + overflow <= overflow_next; always @(posedge wclk or negedge rst_n) if (~rst_n) begin - waddr <= #(1) {ADDR_WIDTH + 1 {1'b0}}; - gcout_reg <= #(1) {ADDR_WIDTH + 1 {1'b0}}; + waddr <= {ADDR_WIDTH + 1 {1'b0}}; + gcout_reg <= {ADDR_WIDTH + 1 {1'b0}}; end else if (wen == 1'b1) begin - waddr <= #(1) waddr_next; - gcout_reg <= #(1) gcout_next; + waddr <= waddr_next; + gcout_reg <= gcout_next; end assign gcout = gcout_reg; generate @@ -431,7 +425,7 @@ default: raddr_next = {ADDR_WIDTH + 1 {1'b0}}; endcase assign ff_waddr = waddr[ADDR_WIDTH - 1:0]; - assign pushflags = (rst_n ? {full, fmo, paf, overflow} : 4'b1111); + assign pushflags = {full, fmo, paf, overflow}; assign waddr_next = waddr + (wmode == 2'h0 ? 'h4 : (wmode == 2'h1 ? 'h2 : 'h1)); endmodule module fifo_pop ( @@ -445,23 +439,24 @@ rmode, wmode, gcin, - depth, upae ); parameter ADDR_WIDTH = 11; parameter FIFO_WIDTH = 3'd2; + parameter DEPTH = 6; output wire ren_o; output wire [3:0] popflags; output reg [ADDR_WIDTH - 1:0] out_raddr; output wire [ADDR_WIDTH:0] gcout; input rst_n; + (* clkbuf_sink *) input rclk; input ren_in; input [1:0] rmode; input [1:0] wmode; input [ADDR_WIDTH:0] gcin; input [ADDR_WIDTH - 1:0] upae; - input [2:0] depth; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; reg empty; reg epo; reg pae; @@ -491,24 +486,14 @@ wire [ADDR_WIDTH:0] raddr_next; wire [ADDR_WIDTH - 1:0] ff_raddr_next; wire [ADDR_WIDTH:0] tmp; - wire [ADDR_WIDTH:0] next_count; - wire [ADDR_WIDTH:0] count; - reg [ADDR_WIDTH:0] fbytes; + wire [ADDR_PLUS_ONE:0] next_count; + wire [ADDR_PLUS_ONE:0] count; + wire [ADDR_PLUS_ONE:0] fbytes; genvar i; assign next_count = waddr - raddr_next; assign count = waddr - raddr; - always @(*) - case (depth) - 3'b000: fbytes = 'd2048; - 3'b001: fbytes = 'd1024; - 3'b010: fbytes = 'd512; - 3'b011: fbytes = 'd256; - 3'b100: fbytes = 'd128; - 3'b101: fbytes = 'd64; - 3'b110: fbytes = 'd32; - 3'b111: fbytes = 'd4096; - endcase - always @(*) pae_thresh = rmode ? (rmode[0] ? upae << 1 : upae) : upae << 2; + assign fbytes = 1 << (DEPTH + 5); + always @(*) pae_thresh = rmode[1] ? upae : (rmode[0] ? upae << 1 : upae << 2); assign ren_out = (empty ? 1'b1 : ren_in); always @(*) case (rmode) @@ -522,8 +507,8 @@ e2 = 1'b0; o1 = 1'b0; o2 = 1'b0; - q1 = next_count < pae_thresh; - q2 = count < pae_thresh; + q1 = next_count < {1'b0, pae_thresh}; + q2 = count < {1'b0, pae_thresh}; case (rmode) 2'h0: begin e1 = raddr_next[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2]; @@ -556,14 +541,14 @@ assign pae_next = (ren_in & !empty ? q1 : q2); always @(posedge rclk or negedge rst_n) if (~rst_n) begin - empty <= #(1) 1'b1; - pae <= #(1) 1'b1; - epo <= #(1) 1'b0; + empty <= 1'b1; + pae <= 1'b1; + epo <= 1'b0; end else begin - empty <= #(1) empty_next; - pae <= #(1) pae_next; - epo <= #(1) epo_next; + empty <= empty_next; + pae <= pae_next; + epo <= epo_next; end assign gc8out_next = (raddr_next >> 1) ^ raddr_next; assign gc16out_next = (raddr_next >> 2) ^ (raddr_next >> 1); @@ -580,20 +565,20 @@ gcout_next = 'h0; always @(posedge rclk or negedge rst_n) if (~rst_n) - waddr <= #(1) 12'h000; + waddr <= 12'h000; else - waddr <= #(1) waddr_next; + waddr <= waddr_next; always @(posedge rclk or negedge rst_n) if (~rst_n) begin - underflow <= #(1) 1'b0; - bwl_sel <= #(1) 2'h0; - gcout_reg <= #(1) 12'h000; + underflow <= 1'b0; + bwl_sel <= 2'h0; + gcout_reg <= 12'h000; end else if (ren_in) begin - underflow <= #(1) empty; + underflow <= empty; if (!empty) begin - bwl_sel <= #(1) raddr_next[1:0]; - gcout_reg <= #(1) gcout_next; + bwl_sel <= raddr_next[1:0]; + gcout_reg <= gcout_next; end end generate @@ -603,32 +588,33 @@ endgenerate always @(*) case (gmode) - 2'h0: waddr_next = {tmp[9:0], 2'b00} & 12'hffc; - 2'h1: waddr_next = {tmp[10:0], 1'b0} & 12'hffe; - 2'h2: waddr_next = {tmp[11:0]} & 12'hfff; - default: waddr_next = 12'h000; + 2'h0: waddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 2'h1: waddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2'h2: waddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_PLUS_ONE {1'b1}}; + default: waddr_next = {ADDR_PLUS_ONE {1'b0}}; endcase assign ff_raddr_next = ff_raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1)); assign raddr_next = raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1)); always @(posedge rclk or negedge rst_n) if (~rst_n) - ff_raddr <= #(1) 1'sb0; + ff_raddr <= 1'sb0; else if (empty & ~empty_next) - ff_raddr <= #(1) raddr_next[10:0]; + ff_raddr <= raddr_next[ADDR_WIDTH - 1:0]; else if ((ren_in & !empty) & ~empty_next) - ff_raddr <= #(1) ff_raddr_next; + ff_raddr <= ff_raddr_next; always @(posedge rclk or negedge rst_n) if (~rst_n) - raddr <= #(1) 12'h000; + raddr <= 12'h000; else if (ren_in & !empty) - raddr <= #(1) raddr_next; + raddr <= raddr_next; always @(*) case (FIFO_WIDTH) + 3'h2: out_raddr = {ff_raddr[ADDR_WIDTH - 1:1], bwl_sel[0]}; + 3'h4: out_raddr = {ff_raddr[ADDR_WIDTH - 1:2], bwl_sel}; default: out_raddr = ff_raddr[ADDR_WIDTH - 1:0]; - 2: out_raddr = {ff_raddr[ADDR_WIDTH - 1:1], bwl_sel[0]}; - 4: out_raddr = {ff_raddr[ADDR_WIDTH - 1:2], bwl_sel}; endcase assign ren_o = ren_out; assign gcout = gcout_reg; assign popflags = {empty, epo, pae, underflow}; endmodule +`default_nettype none