)]}'
{
  "commit": "ccd5cc5017ec4388360addc1747ae1635fca3eca",
  "tree": "d921d027b8b6ebc855608c213790d466593fc0f6",
  "parents": [
    "fc678f9a26d677f09af2b9e8cb95b3ad66e868e9"
  ],
  "author": {
    "name": "Paweł Czarnecki",
    "email": "pczarnecki@antmicro.com",
    "time": "Tue Mar 15 14:32:59 2022 +0100"
  },
  "committer": {
    "name": "Paweł Czarnecki",
    "email": "pczarnecki@antmicro.com",
    "time": "Thu Apr 14 13:05:18 2022 +0200"
  },
  "message": "ql-qlf: update sim modules and techmaps\n\nql-qlf: apply license\nql-qlf: apply clkbuf sink attributes\nql-qlf: TDP36K: s/\\t/    /\nql-qlf: replace uram module with sram1024x18\nql-qlf: change ram_mode and fifo_mode from regs back to wires\nql-qlf: bram sim: remove PL_ signals\nql-qlf: bram sim: remove SCAN_ signals\nql-qlf: k6n10f: sim: remove RAM_ID signal\n\nSigned-off-by: Paweł Czarnecki \u003cpczarnecki@antmicro.com\u003e\n",
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