commit cf91762cf3cd66b69d5a85f2f1ec0cb49ca7bf19
author Rafal Kapuscik <rkapuscik@antmicro.com> Tue Jun 14 10:36:23 2022 +0200
committer Rafal Kapuscik <rkapuscik@antmicro.com> Tue Jun 14 10:36:23 2022 +0200
tree 935965f8f6ea5de2808bd6332c68bfa0ef63233f
parent 3e2fdc2663eeae5ad48ed6609155a5ba289d100f

Use fullSVMode in Surelog

Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>

systemverilog-plugin/uhdmsurelogastfrontend.cc

diff --git a/systemverilog-plugin/uhdmsurelogastfrontend.cc b/systemverilog-plugin/uhdmsurelogastfrontend.cc
index 4a450be..39cc751 100644
--- a/systemverilog-plugin/uhdmsurelogastfrontend.cc
+++ b/systemverilog-plugin/uhdmsurelogastfrontend.cc
@@ -110,6 +110,7 @@
         clp->setParse(true);
         clp->setCompile(true);
         clp->setElaborate(true);
+        clp->fullSVMode(true);
 
         SURELOG::scompiler *compiler = nullptr;
         const std::vector<vpiHandle> uhdm_design = executeCompilation(symbolTable, errors, clp, compiler);