)]}'
{
  "commit": "cf91762cf3cd66b69d5a85f2f1ec0cb49ca7bf19",
  "tree": "935965f8f6ea5de2808bd6332c68bfa0ef63233f",
  "parents": [
    "3e2fdc2663eeae5ad48ed6609155a5ba289d100f"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue Jun 14 10:36:23 2022 +0200"
  },
  "committer": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue Jun 14 10:36:23 2022 +0200"
  },
  "message": "Use fullSVMode in Surelog\n\nSigned-off-by: Rafal Kapuscik \u003crkapuscik@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4a450bee1a09e2af7f902f230cda75f5b8c40f45",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/uhdmsurelogastfrontend.cc",
      "new_id": "39cc7516843a71d787b5236b9ecec451a8518bb0",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/uhdmsurelogastfrontend.cc"
    }
  ]
}