commit d09ffc194ea2f56668bb95b092cbedc93c736473
author Rafal Kapuscik <54976862+rkapuscik@users.noreply.github.com> Fri Apr 15 15:37:30 2022 +0200
committer GitHub <noreply@github.com> Fri Apr 15 15:37:30 2022 +0200
tree 9bf0a448543e5553b0ca92d61e920335d07e97c2
parent 6dc5a76eb36f96a1079a1203f96dce8aa9502c73
parent 040b4fc345d665f78819cd3f7f44a40b750f8f8a

Merge pull request #302 from antmicro/handle-primitives

SystemVerilog: Add handling of primitive gates

systemverilog-plugin/uhdmsurelogastfrontend.cc

diff --git a/systemverilog-plugin/uhdmsurelogastfrontend.cc b/systemverilog-plugin/uhdmsurelogastfrontend.cc
index 82f04e4..1f8472a 100644
--- a/systemverilog-plugin/uhdmsurelogastfrontend.cc
+++ b/systemverilog-plugin/uhdmsurelogastfrontend.cc
@@ -70,10 +70,10 @@
     if (noFErrors == false) {
         noFatalErrors = false;
     }
-    if ((!noFatalErrors) || (!success))
+    if ((!noFatalErrors) || (!success) || (errors->getErrorStats().nbError))
         codedReturn |= 1;
     if (codedReturn) {
-        log_error("Encoraged fatal error when executing Surelog. Aborting!\n");
+        log_error("Error when parsing design. Aborting!\n");
     }
     return the_design;
 }