tree 9bf0a448543e5553b0ca92d61e920335d07e97c2
parent 6dc5a76eb36f96a1079a1203f96dce8aa9502c73
parent 040b4fc345d665f78819cd3f7f44a40b750f8f8a
author Rafal Kapuscik <54976862+rkapuscik@users.noreply.github.com> 1650029850 +0200
committer GitHub <noreply@github.com> 1650029850 +0200
gpgsig -----BEGIN PGP SIGNATURE-----
 
 wsBcBAABCAAQBQJiWXUaCRBK7hj4Ov3rIwAAF4EIADYPZedwJeY89Rgb9/obmniz
 1JnzNjM3pdejh/ZZLY0VP12BnveNsUDic7px2ZOPkmF8n8Ao2SwzYBLV0ADcgzAy
 pK9Q0L97hS0HPWn1boMLa6lHkSUjaCy89t0hkMIWFcmSxhP5US/eVuS2qxUqRxBD
 xnu3xH5EJZDfTjh2b/Z3SP79BkBcJ3BdqUmB3EmKpQOa6Y+gOwAr/DX05nUBVlGq
 a6JgY5b2nQQWAqWXPtdz4QYUQll7uDHp5QLM3sdcXYP9TDx7NP/LVZpDTA8PXlwR
 2Vcc5Y6SrrKPlkvgNdT8TXquwG7B23xuoXHF8tXaIbmVw4ADYs8gGVSrgePIDJc=
 =InbC
 -----END PGP SIGNATURE-----
 

Merge pull request #302 from antmicro/handle-primitives

SystemVerilog: Add handling of primitive gates