)]}'
{
  "commit": "d11a5751998cec71c003b612d35e45e648fc46a1",
  "tree": "dd58b7dfdf8be63b4e3803ae1b8ba4b3cd011170",
  "parents": [
    "0f72816c9904126f3f29838df66e082dd80bb588",
    "4d987efc3d970f1b8da7b80bf63c3486b9e3e2be"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "54976862+rkapuscik@users.noreply.github.com",
    "time": "Tue May 31 15:53:33 2022 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue May 31 15:53:33 2022 +0200"
  },
  "message": "Merge pull request #342 from antmicro/missing-typespecs\n\nSystemverilog: Handle missing typespecs",
  "tree_diff": []
}