Merge pull request #361 from antmicro/k6n10f-readd-dffs
Added back regular D flip-flops and latches for k6n10f
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index feeb46b..ae54ec3 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -124,6 +124,33 @@
endmodule
+(* abc9_flop, lib_whitebox *)
+module dff(
+ output reg Q,
+ input wire D,
+ (* clkbuf_sink *)
+ input wire C
+);
+ initial Q <= 1'b0;
+
+ always @(posedge C)
+ Q <= D;
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dffn(
+ output reg Q,
+ input wire D,
+ (* clkbuf_sink *)
+ input wire C
+);
+ initial Q <= 1'b0;
+
+ always @(negedge C)
+ Q <= D;
+
+endmodule
(* abc9_flop, lib_whitebox *)
module dffsre(
diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 16dd36c..303b1de 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -84,6 +84,11 @@
log(" -no_ff_map\n");
log(" By default ff techmap is turned on. Specifying this switch turns it off.\n");
log("\n");
+ log(" -nosdff\n");
+ log(" By default infer synchronous S/R flip-flops for architectures\n");
+ log(" that support them. \n");
+ log(" Specifying this switch turns it off.\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@@ -97,6 +102,7 @@
bool abcOpt;
bool abc9;
bool noffmap;
+ bool nosdff;
void clear_flags() override
{
@@ -112,6 +118,7 @@
abc9 = true;
noffmap = false;
nodsp = false;
+ nosdff = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -177,6 +184,10 @@
noffmap = true;
continue;
}
+ if (args[argidx] == "-nosdff") {
+ nosdff = true;
+ continue;
+ }
break;
}
@@ -192,6 +203,10 @@
abc9 = false;
}
+ if (family == "qlf_k4n8") {
+ nosdff = true;
+ }
+
if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n");
design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay.
@@ -230,9 +245,13 @@
}
std::string noDFFArgs;
- if (family == "qlf_k4n8") {
- noDFFArgs = " -nodffe -nosdff";
+ if (nosdff) {
+ noDFFArgs += " -nosdff";
}
+ if (family == "qlf_k4n8") {
+ noDFFArgs += " -nodffe";
+ }
+
if (check_label("coarse")) {
run("check");
run("opt -nodffe -nosdff");
@@ -366,7 +385,11 @@
// FIXME: dfflegalize seems to leave $_DLATCH_[NP]_ even if it
// is not allowed. So we allow them and map them later to
// $_DLATCHSR_[NP]NN_.
- run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_SDFFE_?N?P_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0");
+ std::string legalizeArgs = " -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0";
+ if (!nosdff) {
+ legalizeArgs += " -cell $_SDFFE_?N?P_ 0";
+ }
+ run("dfflegalize" + legalizeArgs);
} else if (family == "pp3") {
run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
run("techmap -map +/quicklogic/" + family + "/cells_map.v");
diff --git a/ql-qlf-plugin/tests/dffs/dffs.tcl b/ql-qlf-plugin/tests/dffs/dffs.tcl
index fd75277..4e8792e 100644
--- a/ql-qlf-plugin/tests/dffs/dffs.tcl
+++ b/ql-qlf-plugin/tests/dffs/dffs.tcl
@@ -412,7 +412,7 @@
design -reset
# =============================================================================
-# qlf_k6n10f
+# qlf_k6n10f (with synchronous S/R flip-flops)
read_verilog $::env(DESIGN_TOP).v
design -save read
@@ -719,6 +719,226 @@
design -reset
# =============================================================================
+# qlf_k6n10f (no synchronous S/R flip-flops)
+
+read_verilog $::env(DESIGN_TOP).v
+design -save read
+
+# DFF
+hierarchy -top my_dff
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dff -nosdff
+design -load postopt
+yosys cd my_dff
+stat
+select -assert-count 1 t:dffsre
+
+# DFFN
+design -load read
+hierarchy -top my_dffn
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffn -nosdff
+design -load postopt
+yosys cd my_dffn
+stat
+select -assert-count 1 t:dffnsre
+
+
+# DFFSRE from DFFR_N
+design -load read
+hierarchy -top my_dffr_n
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffr_n -nosdff
+design -load postopt
+yosys cd my_dffr_n
+stat
+select -assert-count 1 t:dffsre
+
+# DFFSRE from DFFR_P
+design -load read
+hierarchy -top my_dffr_p
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffr_p -nosdff
+design -load postopt
+yosys cd my_dffr_p
+stat
+select -assert-count 1 t:dffsre
+select -assert-count 1 t:\$lut
+
+# DFFSRE from DFFRE_N
+design -load read
+hierarchy -top my_dffre_n
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffre_n -nosdff
+design -load postopt
+yosys cd my_dffre_n
+stat
+select -assert-count 1 t:dffsre
+
+# DFFSRE from DFFRE_P
+design -load read
+hierarchy -top my_dffre_p
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffre_p -nosdff
+design -load postopt
+yosys cd my_dffre_p
+stat
+select -assert-count 1 t:dffsre
+select -assert-count 1 t:\$lut
+
+
+# DFFSRE from DFFS_N
+design -load read
+hierarchy -top my_dffs_n
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffs_n -nosdff
+design -load postopt
+yosys cd my_dffs_n
+stat
+select -assert-count 1 t:dffsre
+
+# DFFSRE from DFFS_P
+design -load read
+hierarchy -top my_dffs_p
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffs_p -nosdff
+design -load postopt
+yosys cd my_dffs_p
+stat
+select -assert-count 1 t:dffsre
+select -assert-count 1 t:\$lut
+
+# DFFSRE from DFFSE_N
+design -load read
+hierarchy -top my_dffse_n
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffse_n -nosdff
+design -load postopt
+yosys cd my_dffse_n
+stat
+select -assert-count 1 t:dffsre
+
+# DFFSRE from DFFSE_P
+design -load read
+hierarchy -top my_dffse_p
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffse_p -nosdff
+design -load postopt
+yosys cd my_dffse_p
+stat
+select -assert-count 1 t:dffsre
+select -assert-count 1 t:\$lut
+
+
+# LATCH
+design -load read
+hierarchy -top my_latch
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latch -nosdff
+design -load postopt
+yosys cd my_latch
+stat
+select -assert-count 1 t:latchsre
+
+# LATCHN
+design -load read
+hierarchy -top my_latchn
+yosys proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchn -nosdff
+design -load postopt
+yosys cd my_latchn
+stat
+select -assert-count 1 t:latchnsre
+
+
+## LATCHSRE from LATCHR_N
+#design -load read
+#hierarchy -top my_latchr_n
+#yosys proc
+#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchr_n -nosdff
+#design -load postopt
+#yosys cd my_latchr_n
+#stat
+#select -assert-count 1 t:latchr_n
+#
+## LATCHSRE from LATCHR_P
+#design -load read
+#hierarchy -top my_latchr_p
+#yosys proc
+#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchr_p -nosdff
+#design -load postopt
+#yosys cd my_latchr_p
+#stat
+#select -assert-count 1 t:latchr_p
+#select -assert-count 1 t:\$lut
+#
+## LATCHSRE from LATCHS_N
+#design -load read
+#hierarchy -top my_latchs_n
+#yosys proc
+#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchs_n -nosdff
+#design -load postopt
+#yosys cd my_latchs_n
+#stat
+#select -assert-count 1 t:latchs_n
+#
+## LATCHSRE from LATCHS_P
+#design -load read
+#hierarchy -top my_latchs_p
+#yosys proc
+#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchs_p -nosdff
+#design -load postopt
+#yosys cd my_latchs_p
+#stat
+#select -assert-count 1 t:latchs_p
+#select -assert-count 1 t:\$lut
+#
+#
+## LATCHSRE from LATCHNR_N
+#design -load read
+#hierarchy -top my_latchnr_n
+#yosys proc
+#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchnr_n -nosdff
+#design -load postopt
+#yosys cd my_latchnr_n
+#stat
+#select -assert-count 1 t:latchnr_n
+#
+## LATCHSRE from LATCHNR_P
+#design -load read
+#hierarchy -top my_latchnr_p
+#yosys proc
+#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchnr_p -nosdff
+#design -load postopt
+#yosys cd my_latchnr_p
+#stat
+#select -assert-count 1 t:latchnr_p
+#select -assert-count 1 t:\$lut
+#
+## LATCHSRE from LATCHNS_N
+#design -load read
+#hierarchy -top my_latchns_n
+#yosys proc
+#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchns_n -nosdff
+#design -load postopt
+#yosys cd my_latchns_n
+#stat
+#select -assert-count 1 t:latchns_n
+#
+## LATCHSRE from LATCHNS_P
+#design -load read
+#hierarchy -top my_latchns_p
+#yosys proc
+#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchns_p -nosdff
+#design -load postopt
+#yosys cd my_latchns_p
+#stat
+#select -assert-count 1 t:latchns_p
+#select -assert-count 1 t:\$lut
+
+design -reset
+
+# =============================================================================
# DFF on pp3 device
design -reset
