diff --git a/design_introspection-plugin/tests/Makefile b/design_introspection-plugin/tests/Makefile
index e31bab6..6eed865 100644
--- a/design_introspection-plugin/tests/Makefile
+++ b/design_introspection-plugin/tests/Makefile
@@ -1,7 +1,8 @@
-TESTS = get_nets
+TESTS = get_nets get_ports
 .PHONY: $(TESTS)
 
 get_nets_verify = $(call compare,get_nets,txt)
+get_ports_verify = $(call compare,get_ports,txt)
 
 all: $(TESTS)
 compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.golden.txt b/design_introspection-plugin/tests/get_ports/get_ports.golden.txt
new file mode 100644
index 0000000..16e7e98
--- /dev/null
+++ b/design_introspection-plugin/tests/get_ports/get_ports.golden.txt
@@ -0,0 +1,10 @@
+signal_* ports quiet
+signal_n signal_p
+signal_* ports
+signal_n signal_p
+led ports with filter expression
+led
+Filtered ports
+clk
+All ports
+clk led out_a out_b signal_n signal_p
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.tcl b/design_introspection-plugin/tests/get_ports/get_ports.tcl
new file mode 100644
index 0000000..b71fd65
--- /dev/null
+++ b/design_introspection-plugin/tests/get_ports/get_ports.tcl
@@ -0,0 +1,33 @@
+yosys -import
+plugin -i design_introspection
+#Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+read_verilog get_ports.v
+# Some of symbiflow expects eblifs with only one module.
+synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+help get_ports
+
+set fp [open "get_ports.txt" "w"]
+
+puts "\nsignal_* ports quiet"
+puts $fp "signal_* ports quiet"
+puts $fp [get_ports -quiet signal_*]
+
+puts "\nsignal_* ports"
+puts $fp "signal_* ports"
+puts $fp [get_ports signal_*]
+
+puts "\nled ports with filter expression"
+puts $fp "led ports with filter expression"
+puts $fp [get_ports -filter {mr_ff != true} led]
+
+puts "\nFiltered ports"
+puts $fp "Filtered ports"
+puts $fp [get_ports -filter {mr_ff == true || async_reg == true && dont_touch == true} ]
+
+puts "\nAll ports"
+puts $fp "All ports"
+puts $fp [get_ports]
+
+close $fp
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.v b/design_introspection-plugin/tests/get_ports/get_ports.v
new file mode 100644
index 0000000..d40055b
--- /dev/null
+++ b/design_introspection-plugin/tests/get_ports/get_ports.v
@@ -0,0 +1,75 @@
+module top (
+	(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input  clk,
+	output [3:0] led,
+	inout out_a,
+	output [1:0] out_b,
+	output signal_p,
+	output signal_n
+);
+
+	wire LD6, LD7, LD8, LD9;
+	wire inter_wire, inter_wire_2;
+	localparam BITS = 1;
+	localparam LOG2DELAY = 25;
+
+	reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+	always @(posedge clk) begin
+		counter <= counter + 1;
+	end
+	assign led[1] = inter_wire;
+	assign inter_wire = inter_wire_2;
+	assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
+	OBUFTDS OBUFTDS_2(
+		.I(LD6),
+		.O(signal_p),
+		.OB(signal_n),
+		.T(1'b1)
+	);
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_6(.I(LD6), .O(led[0]));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_7(.I(LD7), .O(inter_wire_2));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_OUT(.I(LD7), .O(out_a));
+	bottom bottom_inst(.I(LD8), .O(led[2]), .OB(out_b));
+	bottom_intermediate bottom_intermediate_inst(.I(LD9), .O(led[3]));
+endmodule
+
+module bottom_intermediate (
+	input I,
+	output O
+);
+	wire bottom_intermediate_wire;
+	assign O = bottom_intermediate_wire;
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_8(.I(I), .O(bottom_intermediate_wire));
+endmodule
+
+module bottom (
+	input I,
+	output [1:0] OB,
+	output O
+);
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_9(.I(I), .O(O));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_10(.I(I), .O(OB[0]));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_11(.I(I), .O(OB[1]));
+endmodule
+