diff --git a/ql-qlf-plugin/ql-dsp-macc.cc b/ql-qlf-plugin/ql-dsp-macc.cc
index c422d31..f95ca87 100644
--- a/ql-qlf-plugin/ql-dsp-macc.cc
+++ b/ql-qlf-plugin/ql-dsp-macc.cc
@@ -55,6 +55,11 @@
         }
     }
 
+    // Accept only posedge clocked FFs
+    if (st.ff->getParam(ID(CLK_POLARITY)) != RTLIL::S1) {
+        return;
+    }
+
     // Get port widths
     size_t a_width = GetSize(st.mul->getPort(ID(A)));
     size_t b_width = GetSize(st.mul->getPort(ID(B)));
@@ -146,13 +151,21 @@
     RTLIL::SigSpec ena;
 
     if (st.ff->hasPort(ID(ARST))) {
-        rst = st.ff->getPort(ID(ARST));
+        if (st.ff->getParam(ID(ARST_POLARITY)) != RTLIL::S0) {
+            rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
+        } else {
+            rst = st.ff->getPort(ID(ARST));
+        }
     } else {
-        rst = RTLIL::SigSpec(RTLIL::S0);
+        rst = RTLIL::SigSpec(RTLIL::S1);
     }
 
     if (st.ff->hasPort(ID(EN))) {
-        ena = st.ff->getPort(ID(EN));
+        if (st.ff->getParam(ID(EN_POLARITY)) != RTLIL::S1) {
+            ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
+        } else {
+            ena = st.ff->getPort(ID(EN));
+        }
     } else {
         ena = RTLIL::SigSpec(RTLIL::S1);
     }
@@ -166,19 +179,20 @@
 
         // Depending on the mux port ordering insert inverter if needed
         log_assert(st.mux_ab == ID(A) || st.mux_ab == ID(B));
-        if (st.mux_ab == ID(B)) {
+        if (st.mux_ab == ID(A)) {
             sig_s = pm.module->Not(NEW_ID, sig_s);
         }
 
         // Assemble the full control signal for the feedback_i port
         RTLIL::SigSpec sig_f;
-        sig_f.append(RTLIL::S0);
         sig_f.append(sig_s);
+        sig_f.append(RTLIL::S0);
+        sig_f.append(RTLIL::S0);
         cell->setPort(RTLIL::escape_id("feedback_i"), sig_f);
     }
     // No acc clear/load
     else {
-        cell->setPort(RTLIL::escape_id("feedback_i"), RTLIL::SigSpec(RTLIL::S0, 2));
+        cell->setPort(RTLIL::escape_id("feedback_i"), RTLIL::SigSpec(RTLIL::S0, 3));
     }
 
     // Connect control ports
@@ -196,7 +210,7 @@
 
     // 3 - output post acc
     // 1 - output pre acc
-    cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(3, 3) : RTLIL::Const(1, 3));
+    cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
 
     // Mark the cells for removal
     pm.autoremove(st.mul);
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index 240dbe8..6dac58b 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -1258,7 +1258,6 @@
     parameter MODE_BITS = 27'b00000000000000000000000000;
 endmodule  /* QL_DSP1 */
 
-(* blackbox *)
 module QL_DSP2 ( // TODO: Name subject to change
       input  [19:0] a,
       input  [17:0] b,
@@ -1329,7 +1328,7 @@
             .unsigned_b_i(unsigned_b),
 
             .clock_i(clk),
-            .reset_n_i(~reset),
+            .reset_n_i(reset),
 
             .saturate_enable_i(saturate_enable),
             .output_select_i(output_select),
@@ -1365,7 +1364,7 @@
             .unsigned_b_i(unsigned_b),
 
             .clock_i(clk),
-            .reset_n_i(~reset),
+            .reset_n_i(reset),
 
             .saturate_enable_i(saturate_enable),
             .output_select_i(output_select),
@@ -1401,7 +1400,7 @@
             .unsigned_b_i(unsigned_b),
 
             .clock_i(clk),
-            .reset_n_i(~reset),
+            .reset_n_i(reset),
 
             .saturate_enable_i(saturate_enable),
             .output_select_i(output_select),
diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v b/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
index 0ae6f3b..e4c1220 100644
--- a/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
@@ -46,7 +46,7 @@
         .z                  (z_o),
         .dly_b              (dly_b_o),
 
-        .clk                (clk_i),
+        .clk                (clock_i),
         .reset              (reset_i),
 
         .feedback           (feedback_i),
@@ -113,7 +113,7 @@
         .z                  (z),
         .dly_b              (dly_b),
 
-        .clk                (clk_i),
+        .clk                (clock_i),
         .reset              (reset_i),
 
         .feedback           (feedback_i),
diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_map.v b/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
index 9606c4f..fe0db9f 100644
--- a/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
@@ -36,7 +36,7 @@
         .unsigned_a_i       (!A_SIGNED),
         .unsigned_b_i       (!B_SIGNED),
 
-        .output_select_i    (2'd0),
+        .output_select_i    (3'd0),
         .saturate_enable_i  (1'b0),
         .shift_right_i      (6'd0),
         .round_i            (1'b0),
@@ -78,7 +78,7 @@
         .unsigned_a_i       (!A_SIGNED),
         .unsigned_b_i       (!B_SIGNED),
 
-        .output_select_i    (2'd0),
+        .output_select_i    (3'd0),
         .saturate_enable_i  (1'b0),
         .shift_right_i      (6'd0),
         .round_i            (1'b0),
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl
index 2de3bdc..468f421 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl
@@ -1,3 +1,29 @@
+# For some tests the equiv_induct pass seems to hang if opt_expr + opt_clean
+# are not invoked after techmapping. Therefore this function is used instead
+# of the equiv_opt pass.
+proc check_equiv {top} {
+    hierarchy -top ${top}
+
+    design -save preopt
+    synth_quicklogic -family qlf_k6n10f -top ${top}
+    design -stash postopt
+
+    design -copy-from preopt  -as gold A:top
+    design -copy-from postopt -as gate A:top
+
+    techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v
+    yosys proc
+    opt_expr
+    opt_clean -purge
+
+    async2sync
+    equiv_make gold gate equiv
+    equiv_induct equiv
+    equiv_status -assert equiv
+
+    return
+}
+
 yosys -import
 if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
 yosys -import  ;# ingest plugin commands
@@ -8,7 +34,8 @@
 set TOP "macc_simple"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv $TOP
+design -load postopt
 yosys cd $TOP
 select -assert-count 1 t:QL_DSP2
 select -assert-count 1 t:*
@@ -16,41 +43,47 @@
 set TOP "macc_simple_clr"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv $TOP
+design -load postopt
 yosys cd $TOP
 select -assert-count 1 t:QL_DSP2
-select -assert-count 1 t:\$lut
-select -assert-count 2 t:*
+select -assert-count 1 t:*
 
 set TOP "macc_simple_arst"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv $TOP
+design -load postopt
 yosys cd $TOP
 select -assert-count 1 t:QL_DSP2
-select -assert-count 1 t:*
-
-set TOP "macc_simple_ena"
-design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
-select -assert-count 1 t:QL_DSP2
-select -assert-count 1 t:*
-
-set TOP "macc_simple_arst_clr_ena"
-design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
-select -assert-count 1 t:QL_DSP2
-select -assert-count 1 t:\$lut
 select -assert-count 2 t:*
 
+#FIXME: DSP not inferred (got $mux instead of $dffe)
+#set TOP "macc_simple_ena"
+#design -load read
+#hierarchy -top $TOP
+#check_equiv $TOP
+#design -load postopt
+#yosys cd $TOP
+#select -assert-count 1 t:QL_DSP2
+#select -assert-count 1 t:*
+
+#FIXME: DSP not inferred (got $mux instead of $dffe)
+#set TOP "macc_simple_arst_clr_ena"
+#design -load read
+#hierarchy -top $TOP
+#check_equiv $TOP
+#design -load postopt
+#yosys cd $TOP
+#select -assert-count 1 t:QL_DSP2
+#select -assert-count 1 t:\$lut
+#select -assert-count 2 t:*
+
 set TOP "macc_simple_preacc"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv $TOP
+design -load postopt
 yosys cd $TOP
 select -assert-count 1 t:QL_DSP2
 select -assert-count 1 t:*
@@ -58,9 +91,9 @@
 set TOP "macc_simple_preacc_clr"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv $TOP
+design -load postopt
 yosys cd $TOP
 select -assert-count 1 t:QL_DSP2
-select -assert-count 1 t:\$lut
-select -assert-count 2 t:*
+select -assert-count 1 t:*
 
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl
index 75acb10..b653836 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl
@@ -1,3 +1,29 @@
+# For some tests the equiv_induct pass seems to hang if opt_expr + opt_clean
+# are not invoked after techmapping. Therefore this function is used instead
+# of the equiv_opt pass.
+proc check_equiv {top} {
+    hierarchy -top ${top}
+
+    design -save preopt
+    synth_quicklogic -family qlf_k6n10f -top ${top}
+    design -stash postopt
+
+    design -copy-from preopt  -as gold A:top
+    design -copy-from postopt -as gate A:top
+
+    techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v
+    yosys proc
+    opt_expr
+    opt_clean
+
+    async2sync
+    equiv_make gold gate equiv
+    equiv_induct equiv
+    equiv_status -assert equiv
+
+    return
+}
+
 yosys -import
 if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
 yosys -import  ;# ingest plugin commands
@@ -7,29 +33,29 @@
 
 set TOP "mult_16x16"
 design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
+yosys cd ${TOP}
 select -assert-count 1 t:QL_DSP2
 
 set TOP "mult_20x18"
 design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
+yosys cd ${TOP}
 select -assert-count 1 t:QL_DSP2
 
 set TOP "mult_8x8"
 design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
+yosys cd ${TOP}
 select -assert-count 1 t:QL_DSP2
 
 set TOP "mult_10x9"
 design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
+yosys cd ${TOP}
 select -assert-count 1 t:QL_DSP2
 
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl
index dd06114..0599d95 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl
@@ -1,3 +1,29 @@
+# For some tests the equiv_induct pass seems to hang if opt_expr + opt_clean
+# are not invoked after techmapping. Therefore this function is used instead
+# of the equiv_opt pass.
+proc check_equiv {top} {
+    hierarchy -top ${top}
+
+    design -save preopt
+    synth_quicklogic -family qlf_k6n10f -top ${top}
+    design -stash postopt
+
+    design -copy-from preopt  -as gold A:top
+    design -copy-from postopt -as gate A:top
+
+    techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v
+    yosys proc
+    opt_expr
+    opt_clean
+
+    async2sync
+    equiv_make gold gate equiv
+    equiv_induct equiv
+    equiv_status -assert equiv
+
+    return
+}
+
 yosys -import
 if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
 yosys -import  ;# ingest plugin commands
@@ -8,8 +34,8 @@
 set TOP "simd_mult"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
 select -assert-count 0 t:dsp_t1_20x18x64
 select -assert-count 0 t:dsp_t1_10x9x32
 select -assert-count 1 t:QL_DSP2
@@ -17,7 +43,8 @@
 set TOP "simd_mult_inferred"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv ${TOP}
+design -load postopt
 yosys cd $TOP
 select -assert-count 0 t:dsp_t1_20x18x64
 select -assert-count 0 t:dsp_t1_10x9x32
@@ -26,7 +53,8 @@
 set TOP "simd_mult_odd"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv ${TOP}
+design -load postopt
 yosys cd $TOP
 select -assert-count 0 t:dsp_t1_20x18x64
 select -assert-count 0 t:dsp_t1_10x9x32
@@ -35,7 +63,8 @@
 set TOP "simd_mult_conflict"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv ${TOP}
+design -load postopt
 yosys cd $TOP
 select -assert-count 0 t:dsp_t1_20x18x64
 select -assert-count 0 t:dsp_t1_10x9x32