Merge pull request #353 from antmicro/werror
Force -Werror in CI, fix various warnings
diff --git a/.github/workflows/build-and-test.sh b/.github/workflows/build-and-test.sh
old mode 100644
new mode 100755
index 2d913b0..7d0401e
--- a/.github/workflows/build-and-test.sh
+++ b/.github/workflows/build-and-test.sh
@@ -23,7 +23,10 @@
start_section Building
+export CXXFLAGS=-Werror
make UHDM_INSTALL_DIR=`pwd`/env/conda/envs/yosys-plugins/ plugins -j`nproc`
+unset CXXFLAGS
+
end_section
##########################################################################
diff --git a/ql-qlf-plugin/ql-bram-split.cc b/ql-qlf-plugin/ql-bram-split.cc
index f701dcf..f699ee5 100644
--- a/ql-qlf-plugin/ql-bram-split.cc
+++ b/ql-qlf-plugin/ql-bram-split.cc
@@ -162,11 +162,6 @@
groups[key].push_back(cell);
}
- for (const auto &it : groups) {
- const auto &group = it.second;
- const auto &config = it.first;
- }
-
std::vector<const RTLIL::Cell *> cellsToRemove;
// Map cell pairs to the target BRAM 2x18 cell
diff --git a/ql-qlf-plugin/ql-dsp-io-regs.cc b/ql-qlf-plugin/ql-dsp-io-regs.cc
index d65a06f..9f24594 100644
--- a/ql-qlf-plugin/ql-dsp-io-regs.cc
+++ b/ql-qlf-plugin/ql-dsp-io-regs.cc
@@ -82,7 +82,7 @@
for (auto portname : ports2del) {
const RTLIL::SigSpec *port = &dsp->getPort(RTLIL::escape_id(portname));
if (!port)
- log_error("%s port not found!", portname);
+ log_error("%s port not found!", portname.c_str());
dsp->connections_.erase(RTLIL::escape_id(portname));
}
}
diff --git a/ql-qlf-plugin/ql-edif.cc b/ql-qlf-plugin/ql-edif.cc
index 4633a10..a560c1e 100644
--- a/ql-qlf-plugin/ql-edif.cc
+++ b/ql-qlf-plugin/ql-edif.cc
@@ -250,14 +250,12 @@
}
int width = port_it.second;
int start = 0;
- bool upto = false;
auto m = design->module(cell_it.first);
if (m) {
auto w = m->wire(port_it.first);
if (w) {
width = GetSize(w);
start = w->start_offset;
- upto = w->upto;
}
}
if (width == 1)
