)]}'
{
  "commit": "d5602a1f19872066c89fa0749e75a233ea0319f0",
  "tree": "a94a3b12001d2e88c9afdc0d5d7ae2c659f31e92",
  "parents": [
    "ddd19038cf215eb5c1e3858fd82564d0aa825bf8"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Mon Mar 27 11:35:10 2023 +0200"
  },
  "committer": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Wed Apr 05 15:57:48 2023 +0200"
  },
  "message": "systemverilog-plugin: Use AstNode:: members correctly\n\nSigned-off-by: Magdalena Andrys \u003cmandrys@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "71d15a4d0b6d0ae3bc816d5abdb8517898406d9f",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/third_party/yosys/simplify.cc",
      "new_id": "2f60ce4c8dab26bab1d6d225cbd9d382b63bb97a",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/third_party/yosys/simplify.cc"
    }
  ]
}