)]}'
{
  "commit": "d59859c7ec043612138a9fb335dfd6009dac2f06",
  "tree": "8a19a1da8f10dbde860d95bc247bf02755552248",
  "parents": [
    "2cb0c4767ce027387166394a0171a8e2f9524e37"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Thu Dec 15 12:13:06 2022 +0100"
  },
  "committer": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Wed Dec 28 13:41:24 2022 +0100"
  },
  "message": "systemverilog-plugin: Visit vpiContAssign for module instance in uhdmtopModules\n\nSigned-off-by: Magdalena Andrys \u003cmandrys@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c7f799dd7cd57020e5753b18606c60f2627f49d1",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "6c508360525162057ee99669a7987d37d727dfcc",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}