Merge pull request #130 from antmicro/add-new-write-edif-backend
ql: edif: add padding to LUT INITs
diff --git a/README.md b/README.md
index 4721300..0e3fc84 100644
--- a/README.md
+++ b/README.md
@@ -63,6 +63,7 @@
The plugin adds the following command:
* synth_quicklogic
+* ql_dsp
Detailed help on the supported command(s) can be obtained by running `help <command_name>` in Yosys.
diff --git a/ql-qlf-plugin/Makefile b/ql-qlf-plugin/Makefile
index 9886c83..e2fa3e1 100644
--- a/ql-qlf-plugin/Makefile
+++ b/ql-qlf-plugin/Makefile
@@ -16,44 +16,44 @@
include ../Makefile_plugin.common
COMMON = common
-QLF_K4N8_DIR = ql-qlf-k4n8
-QLF_K6N10_DIR = ql-qlf-k6n10
+QLF_K4N8_DIR = qlf_k4n8
+QLF_K6N10_DIR = qlf_k6n10
PP3_DIR = pp3
-VERILOG_MODULES = $(COMMON)/cells_sim.v \
- $(QLF_K4N8_DIR)/qlf_k4n8_arith_map.v \
- $(QLF_K4N8_DIR)/qlf_k4n8_cells_sim.v \
- $(QLF_K4N8_DIR)/qlf_k4n8_ffs_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_arith_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_brams_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_brams.txt \
- $(QLF_K6N10_DIR)/qlf_k6n10_cells_sim.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_ffs_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_dsp_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_lut_map.v \
- $(PP3_DIR)/pp3_abc9_map.v \
- $(PP3_DIR)/pp3_abc9_model.v \
- $(PP3_DIR)/pp3_abc9_unmap.v \
- $(PP3_DIR)/pp3_cells_map.v \
- $(PP3_DIR)/pp3_cells_sim.v \
- $(PP3_DIR)/pp3_ffs_map.v \
- $(PP3_DIR)/pp3_latches_map.v \
- $(PP3_DIR)/pp3_lut_map.v \
- $(PP3_DIR)/pp3_lutdefs.txt \
- $(PP3_DIR)/pp3_brams_sim.v \
- $(PP3_DIR)/pp3_brams_map.v \
- $(PP3_DIR)/pp3_brams.txt \
- $(PP3_DIR)/pp3_bram_init_8_16.vh \
- $(PP3_DIR)/pp3_bram_init_32.vh \
- $(PP3_DIR)/pp3_qlal4s3b_sim.v \
- $(PP3_DIR)/pp3_mult_sim.v \
- $(PP3_DIR)/pp3_qlal3_sim.v \
+VERILOG_MODULES = $(COMMON)/cells_sim.v \
+ $(QLF_K4N8_DIR)/arith_map.v \
+ $(QLF_K4N8_DIR)/cells_sim.v \
+ $(QLF_K4N8_DIR)/ffs_map.v \
+ $(QLF_K6N10_DIR)/arith_map.v \
+ $(QLF_K6N10_DIR)/brams_map.v \
+ $(QLF_K6N10_DIR)/brams.txt \
+ $(QLF_K6N10_DIR)/cells_sim.v \
+ $(QLF_K6N10_DIR)/ffs_map.v \
+ $(QLF_K6N10_DIR)/dsp_map.v \
+ $(QLF_K6N10_DIR)/lut_map.v \
+ $(PP3_DIR)/abc9_map.v \
+ $(PP3_DIR)/abc9_model.v \
+ $(PP3_DIR)/abc9_unmap.v \
+ $(PP3_DIR)/cells_map.v \
+ $(PP3_DIR)/cells_sim.v \
+ $(PP3_DIR)/ffs_map.v \
+ $(PP3_DIR)/latches_map.v \
+ $(PP3_DIR)/lut_map.v \
+ $(PP3_DIR)/lutdefs.txt \
+ $(PP3_DIR)/brams_sim.v \
+ $(PP3_DIR)/brams_map.v \
+ $(PP3_DIR)/brams.txt \
+ $(PP3_DIR)/bram_init_8_16.vh \
+ $(PP3_DIR)/bram_init_32.vh \
+ $(PP3_DIR)/qlal4s3b_sim.v \
+ $(PP3_DIR)/mult_sim.v \
+ $(PP3_DIR)/qlal3_sim.v \
retrieve-pmgen:=$(shell mkdir -p pmgen && wget -nc -O pmgen/pmgen.py https://raw.githubusercontent.com/SymbiFlow/yosys/master%2Bwip/passes/pmgen/pmgen.py)
pre-build:=$(shell python3 pmgen/pmgen.py -o pmgen/ql-dsp-pm.h -p ql_dsp ql_dsp.pmg)
install_modules: $(VERILOG_MODULES)
- $(foreach f,$^,install -D $(f) $(DATA_DIR)/quicklogic/$(notdir $(f));)
+ $(foreach f,$^,install -D $(f) $(DATA_DIR)/quicklogic/$(f);)
install: install_modules
diff --git a/ql-qlf-plugin/pp3/pp3_abc9_map.v b/ql-qlf-plugin/pp3/abc9_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_abc9_map.v
rename to ql-qlf-plugin/pp3/abc9_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_abc9_model.v b/ql-qlf-plugin/pp3/abc9_model.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_abc9_model.v
rename to ql-qlf-plugin/pp3/abc9_model.v
diff --git a/ql-qlf-plugin/pp3/pp3_abc9_unmap.v b/ql-qlf-plugin/pp3/abc9_unmap.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_abc9_unmap.v
rename to ql-qlf-plugin/pp3/abc9_unmap.v
diff --git a/ql-qlf-plugin/pp3/pp3_bram_init_32.vh b/ql-qlf-plugin/pp3/bram_init_32.vh
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_bram_init_32.vh
rename to ql-qlf-plugin/pp3/bram_init_32.vh
diff --git a/ql-qlf-plugin/pp3/pp3_bram_init_8_16.vh b/ql-qlf-plugin/pp3/bram_init_8_16.vh
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_bram_init_8_16.vh
rename to ql-qlf-plugin/pp3/bram_init_8_16.vh
diff --git a/ql-qlf-plugin/pp3/pp3_brams.txt b/ql-qlf-plugin/pp3/brams.txt
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_brams.txt
rename to ql-qlf-plugin/pp3/brams.txt
diff --git a/ql-qlf-plugin/pp3/pp3_brams_map.v b/ql-qlf-plugin/pp3/brams_map.v
similarity index 99%
rename from ql-qlf-plugin/pp3/pp3_brams_map.v
rename to ql-qlf-plugin/pp3/brams_map.v
index 7e34cd3..1941a3d 100644
--- a/ql-qlf-plugin/pp3/pp3_brams_map.v
+++ b/ql-qlf-plugin/pp3/brams_map.v
@@ -71,7 +71,7 @@
generate
if (CFG_DBITS <= 16) begin
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_32.vh"
+ `include "bram_init_32.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR),
.A1_1(GND),
@@ -138,7 +138,7 @@
);
end else if (CFG_DBITS <= 32) begin
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_32.vh"
+ `include "bram_init_32.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR),
.A1_1(GND),
@@ -287,7 +287,7 @@
end
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_8_16.vh"
+ `include "bram_init_8_16.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR_11),
.A1_1(GND),
diff --git a/ql-qlf-plugin/pp3/pp3_brams_sim.v b/ql-qlf-plugin/pp3/brams_sim.v
similarity index 99%
rename from ql-qlf-plugin/pp3/pp3_brams_sim.v
rename to ql-qlf-plugin/pp3/brams_sim.v
index 4d1822a..2795852 100644
--- a/ql-qlf-plugin/pp3/pp3_brams_sim.v
+++ b/ql-qlf-plugin/pp3/brams_sim.v
@@ -2129,7 +2129,7 @@
endgenerate
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_8_16.vh"
+ `include "bram_init_8_16.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
@@ -2332,7 +2332,7 @@
if (data_width_int <= 16) begin
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_8_16.vh"
+ `include "bram_init_8_16.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
@@ -2409,7 +2409,7 @@
end else if (data_width_int > 16) begin
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_32.vh"
+ `include "bram_init_32.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
diff --git a/ql-qlf-plugin/pp3/pp3_cells_map.v b/ql-qlf-plugin/pp3/cells_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_cells_map.v
rename to ql-qlf-plugin/pp3/cells_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_cells_sim.v b/ql-qlf-plugin/pp3/cells_sim.v
similarity index 98%
rename from ql-qlf-plugin/pp3/pp3_cells_sim.v
rename to ql-qlf-plugin/pp3/cells_sim.v
index abf6e3a..e498d4e 100644
--- a/ql-qlf-plugin/pp3/pp3_cells_sim.v
+++ b/ql-qlf-plugin/pp3/cells_sim.v
@@ -479,11 +479,11 @@
endmodule
// Include simulation models of QLAL4S3B eFPGA interface
-`include "pp3_qlal4s3b_sim.v"
+`include "qlal4s3b_sim.v"
// Include simulation models for QLAL3 hard blocks
-`include "pp3_qlal3_sim.v"
+`include "qlal3_sim.v"
// Include BRAM and FIFO simulation models
-`include "pp3_brams_sim.v"
+`include "brams_sim.v"
// Include MULT simulation models
-`include "pp3_mult_sim.v"
+`include "mult_sim.v"
diff --git a/ql-qlf-plugin/pp3/pp3_ffs_map.v b/ql-qlf-plugin/pp3/ffs_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_ffs_map.v
rename to ql-qlf-plugin/pp3/ffs_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_latches_map.v b/ql-qlf-plugin/pp3/latches_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_latches_map.v
rename to ql-qlf-plugin/pp3/latches_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_lut_map.v b/ql-qlf-plugin/pp3/lut_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_lut_map.v
rename to ql-qlf-plugin/pp3/lut_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_lutdefs.txt b/ql-qlf-plugin/pp3/lutdefs.txt
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_lutdefs.txt
rename to ql-qlf-plugin/pp3/lutdefs.txt
diff --git a/ql-qlf-plugin/pp3/pp3_mult_sim.v b/ql-qlf-plugin/pp3/mult_sim.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_mult_sim.v
rename to ql-qlf-plugin/pp3/mult_sim.v
diff --git a/ql-qlf-plugin/pp3/pp3_qlal3_sim.v b/ql-qlf-plugin/pp3/qlal3_sim.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_qlal3_sim.v
rename to ql-qlf-plugin/pp3/qlal3_sim.v
diff --git a/ql-qlf-plugin/pp3/pp3_qlal4s3b_sim.v b/ql-qlf-plugin/pp3/qlal4s3b_sim.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_qlal4s3b_sim.v
rename to ql-qlf-plugin/pp3/qlal4s3b_sim.v
diff --git a/ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_arith_map.v b/ql-qlf-plugin/qlf_k4n8/arith_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_arith_map.v
rename to ql-qlf-plugin/qlf_k4n8/arith_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_cells_sim.v b/ql-qlf-plugin/qlf_k4n8/cells_sim.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_cells_sim.v
rename to ql-qlf-plugin/qlf_k4n8/cells_sim.v
diff --git a/ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_ffs_map.v b/ql-qlf-plugin/qlf_k4n8/ffs_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_ffs_map.v
rename to ql-qlf-plugin/qlf_k4n8/ffs_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_arith_map.v b/ql-qlf-plugin/qlf_k6n10/arith_map.v
similarity index 66%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_arith_map.v
rename to ql-qlf-plugin/qlf_k6n10/arith_map.v
index 2d8dee5..6b275d3 100644
--- a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_arith_map.v
+++ b/ql-qlf-plugin/qlf_k6n10/arith_map.v
@@ -38,10 +38,30 @@
endgenerate
wire [Y_WIDTH: 0 ] CARRY;
- assign CARRY[0] = CI;
+
+ // Due to VPR limitations regarding IO connexion to carry chain,
+ // we generate the carry chain input signal using an intermediate adder
+ // since we can connect a & b from io pads, but not cin & cout
+ generate
+ adder intermediate_adder (
+ .cin ( ),
+ .cout (CARRY[0]),
+ .a (CI ),
+ .b (CI ),
+ .sumout ( )
+ );
+
+ adder first_adder (
+ .cin (CARRY[0]),
+ .cout (CARRY[1]),
+ .a (AA[0] ),
+ .b (BB[0] ),
+ .sumout (Y[0] )
+ );
+ endgenerate
genvar i;
- generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
+ generate for (i = 1; i < Y_WIDTH - 1; i = i+1) begin:gen3
adder my_adder (
.cin (CARRY[i] ),
.cout (CARRY[i+1]),
@@ -50,19 +70,6 @@
.sumout (Y[i] )
);
end endgenerate
-
- generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
- assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
- end else begin:gen5
- adder my_adder (
- .cin (CARRY[Y_WIDTH - 1]),
- .cout (CARRY[Y_WIDTH] ),
- .a (1'b0 ),
- .b (1'b0 ),
- .sumout (Y[Y_WIDTH -1] )
- );
- end
- endgenerate
assign X = AA ^ BB;
endmodule
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_brams.txt b/ql-qlf-plugin/qlf_k6n10/brams.txt
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_brams.txt
rename to ql-qlf-plugin/qlf_k6n10/brams.txt
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_brams_map.v b/ql-qlf-plugin/qlf_k6n10/brams_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_brams_map.v
rename to ql-qlf-plugin/qlf_k6n10/brams_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_cells_sim.v b/ql-qlf-plugin/qlf_k6n10/cells_sim.v
similarity index 99%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_cells_sim.v
rename to ql-qlf-plugin/qlf_k6n10/cells_sim.v
index 36872ce..ad22df3 100644
--- a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10/cells_sim.v
@@ -63,7 +63,7 @@
assign lut4_out[2] = s4[2];
assign lut4_out[3] = s4[3];
- assign lut5_out[0] = s0[0];
+ assign lut5_out[0] = s5[0];
assign lut5_out[1] = s5[1];
assign lut6_out = li[5] ? s5[0] : s5[1];
@@ -182,7 +182,7 @@
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input S,
- input E,
+ input E
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_dsp_map.v b/ql-qlf-plugin/qlf_k6n10/dsp_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_dsp_map.v
rename to ql-qlf-plugin/qlf_k6n10/dsp_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_ffs_map.v b/ql-qlf-plugin/qlf_k6n10/ffs_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_ffs_map.v
rename to ql-qlf-plugin/qlf_k6n10/ffs_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_lut_map.v b/ql-qlf-plugin/qlf_k6n10/lut_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_lut_map.v
rename to ql-qlf-plugin/qlf_k6n10/lut_map.v
diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 4a9abc5..36c3afe 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -190,9 +190,9 @@
{
if (check_label("begin")) {
std::string readVelArgs;
- readVelArgs = " +/quicklogic/" + family + "_cells_sim.v";
+ readVelArgs = " +/quicklogic/" + family + "/cells_sim.v";
- run("read_verilog -lib -specify +/quicklogic/cells_sim.v" + readVelArgs);
+ run("read_verilog -lib -specify +/quicklogic/common/cells_sim.v" + readVelArgs);
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
@@ -221,7 +221,7 @@
run("memory_dff");
run("wreduce t:$mul");
run("techmap -map +/mul2dsp.v -map +/quicklogic/" + family +
- "_dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
+ "/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
"-D DSP_NAME=$__MUL16X16",
"(if -no_dsp)");
@@ -245,11 +245,11 @@
}
if (check_label("map_bram", "(skip if -no_bram)") && (family == "qlf_k6n10" || family == "pp3") && inferBram) {
- run("memory_bram -rules +/quicklogic/" + family + "_brams.txt");
+ run("memory_bram -rules +/quicklogic/" + family + "/brams.txt");
if (family == "pp3") {
run("pp3_braminit");
}
- run("techmap -map +/quicklogic/" + family + "_brams_map.v");
+ run("techmap -map +/quicklogic/" + family + "/brams_map.v");
}
if (check_label("map_ffram")) {
@@ -262,7 +262,7 @@
if (check_label("map_gates")) {
if (inferAdder && (family == "qlf_k4n8" || family == "qlf_k6n10")) {
- run("techmap -map +/techmap.v -map +/quicklogic/" + family + "_arith_map.v");
+ run("techmap -map +/techmap.v -map +/quicklogic/" + family + "/arith_map.v");
} else {
run("techmap");
}
@@ -289,9 +289,9 @@
// $_DLATCH_SRPPP_ 0");
} else if (family == "pp3") {
run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
- run("techmap -map +/quicklogic/" + family + "_cells_map.v");
+ run("techmap -map +/quicklogic/" + family + "/cells_map.v");
}
- std::string techMapArgs = " -map +/techmap.v -map +/quicklogic/" + family + "_ffs_map.v";
+ std::string techMapArgs = " -map +/techmap.v -map +/quicklogic/" + family + "/ffs_map.v";
if (!noffmap) {
run("techmap " + techMapArgs);
}
@@ -310,14 +310,14 @@
} else if (family == "qlf_k4n8") {
run("abc -lut 4 ");
} else if (family == "pp3") {
- run("techmap -map +/quicklogic/" + family + "_latches_map.v");
+ run("techmap -map +/quicklogic/" + family + "/latches_map.v");
if (abc9) {
- run("read_verilog -lib -specify -icells +/quicklogic/" + family + "_abc9_model.v");
- run("techmap -map +/quicklogic/" + family + "_abc9_map.v");
+ run("read_verilog -lib -specify -icells +/quicklogic/" + family + "/abc9_model.v");
+ run("techmap -map +/quicklogic/" + family + "/abc9_map.v");
run("abc9 -maxlut 4 -dff");
- run("techmap -map +/quicklogic/" + family + "_abc9_unmap.v");
+ run("techmap -map +/quicklogic/" + family + "/abc9_unmap.v");
} else {
- std::string lutDefs = "+/quicklogic/" + family + "_lutdefs.txt";
+ std::string lutDefs = "+/quicklogic/" + family + "/lutdefs.txt";
rewrite_filename(lutDefs);
std::string abcArgs = "+read_lut," + lutDefs +
@@ -336,7 +336,7 @@
if (check_label("map_cells") && (family == "qlf_k6n10" || family == "pp3")) {
std::string techMapArgs;
- techMapArgs = "-map +/quicklogic/" + family + "_lut_map.v";
+ techMapArgs = "-map +/quicklogic/" + family + "/lut_map.v";
run("techmap " + techMapArgs);
run("clean");
}
diff --git a/ql-qlf-plugin/tests/dffs/dffs.tcl b/ql-qlf-plugin/tests/dffs/dffs.tcl
index 9b1941c..d96b3e6 100644
--- a/ql-qlf-plugin/tests/dffs/dffs.tcl
+++ b/ql-qlf-plugin/tests/dffs/dffs.tcl
@@ -8,7 +8,7 @@
# DFF
hierarchy -top my_dff
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8 -top my_dff
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8 -top my_dff
design -load postopt
yosys cd my_dff
stat
@@ -163,7 +163,7 @@
# DFF
hierarchy -top my_dff
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top my_dff
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top my_dff
design -load postopt
yosys cd my_dff
stat
@@ -412,7 +412,7 @@
# DFF
hierarchy -top my_dff
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dff
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dff
design -load postopt
yosys cd my_dff
stat
@@ -427,7 +427,7 @@
design -load read
hierarchy -top my_dffe
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffe
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffe
design -load postopt
yosys cd my_dffe
stat
@@ -441,7 +441,7 @@
design -load read
hierarchy -top my_dffr_p
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffr_p
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffr_p
design -load postopt
yosys cd my_dffr_p
stat
@@ -458,7 +458,7 @@
design -load read
hierarchy -top my_dffr_n
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffr_n
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffr_n
design -load postopt
yosys cd my_dffr_n
stat
@@ -476,7 +476,7 @@
design -load read
hierarchy -top my_dffs_clk_p
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffs_clk_p
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffs_clk_p
design -load postopt
yosys cd my_dffs_clk_p
stat
@@ -494,7 +494,7 @@
design -load read
hierarchy -top my_dffs_clk_n
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffs_clk_n
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffs_clk_n
design -load postopt
yosys cd my_dffs_clk_n
stat
diff --git a/ql-qlf-plugin/tests/fsm/fsm.tcl b/ql-qlf-plugin/tests/fsm/fsm.tcl
index d6d72e2..2e09677 100644
--- a/ql-qlf-plugin/tests/fsm/fsm.tcl
+++ b/ql-qlf-plugin/tests/fsm/fsm.tcl
@@ -9,7 +9,7 @@
yosys proc
flatten
-equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -run :prove -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
async2sync
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
diff --git a/ql-qlf-plugin/tests/full_adder/full_adder.tcl b/ql-qlf-plugin/tests/full_adder/full_adder.tcl
index 3093086..9c5a402 100644
--- a/ql-qlf-plugin/tests/full_adder/full_adder.tcl
+++ b/ql-qlf-plugin/tests/full_adder/full_adder.tcl
@@ -6,7 +6,7 @@
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top full_adder
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8
design -reset
@@ -14,24 +14,29 @@
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top subtractor
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8
design -reset
+
# Equivalence check for adder synthesis for qlf-k6n10
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top full_adder
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10
+synth_quicklogic -family qlf_k6n10
+yosys cd full_adder
+stat
+select -assert-count 5 t:adder
design -reset
-#TODO: Fix equivalence check for substractor design with qlf_k6n10 device
-
-## Equivalence check for subtractor synthesis
-#read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
-#hierarchy -check -top subtractor
-#yosys proc
-#equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10
+# Equivalence check for subtractor synthesis for qlf-k6n10
+read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
+hierarchy -check -top subtractor
+yosys proc
+synth_quicklogic -family qlf_k6n10
+yosys cd subtractor
+stat
+select -assert-count 5 t:adder
design -reset
@@ -39,7 +44,7 @@
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top full_adder
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd full_adder
@@ -58,7 +63,7 @@
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top subtractor
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd subtractor
diff --git a/ql-qlf-plugin/tests/logic/logic.tcl b/ql-qlf-plugin/tests/logic/logic.tcl
index 6bfb7cb..0e10db5 100644
--- a/ql-qlf-plugin/tests/logic/logic.tcl
+++ b/ql-qlf-plugin/tests/logic/logic.tcl
@@ -6,7 +6,7 @@
read_verilog $::env(DESIGN_TOP).v
hierarchy -top top
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8
design -load postopt
yosys cd top
@@ -19,7 +19,7 @@
read_verilog $::env(DESIGN_TOP).v
hierarchy -top top
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10
design -load postopt
yosys cd top
@@ -32,7 +32,7 @@
read_verilog $::env(DESIGN_TOP).v
hierarchy -top top
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd top
diff --git a/ql-qlf-plugin/tests/logic/logic.ys b/ql-qlf-plugin/tests/logic/logic.ys
index c7f0cd5..037896c 100644
--- a/ql-qlf-plugin/tests/logic/logic.ys
+++ b/ql-qlf-plugin/tests/logic/logic.ys
@@ -2,7 +2,7 @@
read_verilog ./logic.v
hierarchy -top top
proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8
design -load postopt
cd top
diff --git a/ql-qlf-plugin/tests/mux/mux.tcl b/ql-qlf-plugin/tests/mux/mux.tcl
index 260e242..47a1e1b 100644
--- a/ql-qlf-plugin/tests/mux/mux.tcl
+++ b/ql-qlf-plugin/tests/mux/mux.tcl
@@ -7,7 +7,7 @@
hierarchy -top mux2
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd mux2
select -assert-count 1 t:LUT3
@@ -19,7 +19,7 @@
design -load read
hierarchy -top mux4
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd mux4
select -assert-count 3 t:LUT3
@@ -31,7 +31,7 @@
design -load read
hierarchy -top mux8
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd mux8
select -assert-count 1 t:LUT1
@@ -45,7 +45,7 @@
design -load read
hierarchy -top mux16
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd mux16
select -assert-count 1 t:LUT3
diff --git a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys
index 5539004..20228ca 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys
+++ b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys
@@ -8,7 +8,7 @@
hierarchy -top BRAM_32x512
proc
memory
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_32x512
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_32x512
design -load postopt
cd BRAM_32x512
stat
@@ -19,7 +19,7 @@
hierarchy -top BRAM_32x512
proc
memory
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_16x1024
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_16x1024
design -load postopt
cd BRAM_16x1024
stat
@@ -30,7 +30,7 @@
hierarchy -top BRAM_8x2048
proc
memory
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_8x2048
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_8x2048
design -load postopt
cd BRAM_8x2048
stat
@@ -41,7 +41,7 @@
hierarchy -top BRAM_4x4096
proc
memory
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_4x4096
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_4x4096
design -load postopt
cd BRAM_4x4096
stat
diff --git a/ql-qlf-plugin/tests/tribuf/tribuf.tcl b/ql-qlf-plugin/tests/tribuf/tribuf.tcl
index 067e7fd..acee086 100644
--- a/ql-qlf-plugin/tests/tribuf/tribuf.tcl
+++ b/ql-qlf-plugin/tests/tribuf/tribuf.tcl
@@ -9,7 +9,7 @@
tribuf
flatten
synth
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/simcells.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/simcells.v synth_quicklogic -family pp3
design -load postopt
yosys cd tristate
select -assert-count 2 t:inpad
diff --git a/xdc-plugin/tests/Makefile b/xdc-plugin/tests/Makefile
index 363cbfe..f96a6f1 100644
--- a/xdc-plugin/tests/Makefile
+++ b/xdc-plugin/tests/Makefile
@@ -8,12 +8,14 @@
# counter - basic test for IOSTANDARD, SLEW, DRIVE, IN_TERM properties
# counter-dict - basic test using XDC -dict for IOSTANDARD, SLEW, DRIVE, IN_TERM properties
+# package_pins-dict-space - basic test for variable whitespace between PACKAGE_PINs and IOSTANDARD
# port_indexes - like counter but bus port indices are passes without curly braces
# io_loc_pairs - test for LOC property being set on IOBUFs as the IO_LOC_PAIRS parameter
# minilitex_ddr_arty - litex design with more types of IOBUFS including differential
# package_pins - test for PACKAGE_PIN property being set on IOBUFs as the IO_LOC_PAIRS parameter
TESTS = counter \
counter-dict \
+ package_pins-dict-space \
port_indexes \
io_loc_pairs \
minilitex_ddr_arty \
@@ -34,3 +36,4 @@
io_loc_pairs_verify = $(call json_test,io_loc_pairs)
minilitex_ddr_arty_verify = $(call json_test,minilitex_ddr_arty)
package_pins_verify = $(call json_test,package_pins)
+package_pins-dict-space_verify = $(call json_test,package_pins-dict-space)
diff --git a/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.golden.json b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.golden.json
new file mode 100644
index 0000000..2e9102d
--- /dev/null
+++ b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.golden.json
@@ -0,0 +1,47 @@
+{
+ "OBUFTDS_2": {
+ "IOSTANDARD": "DIFF_SSTL135",
+ "IO_LOC_PAIRS": "signal_p:N2,signal_n:N1",
+ "SLEW": "FAST"
+ },
+ "OBUF_6": {
+ "DRIVE": "12",
+ "IOSTANDARD": "LVCMOS33",
+ "IO_LOC_PAIRS": "led[0]:D10",
+ "SLEW": "SLOW"
+ },
+ "OBUF_7": {
+ "IN_TERM": "UNTUNED_SPLIT_40",
+ "IOSTANDARD": "SSTL135",
+ "IO_LOC_PAIRS": "led[1]:A9",
+ "SLEW": "FAST"
+ },
+ "OBUF_OUT": {
+ "IN_TERM": "UNTUNED_SPLIT_50",
+ "IOSTANDARD": "LVCMOS33",
+ "IO_LOC_PAIRS": "out_a:E3",
+ "SLEW": "FAST"
+ },
+ "bottom_inst.OBUF_10": {
+ "IOSTANDARD": "LVCMOS18",
+ "IO_LOC_PAIRS": "out_b[0]:C2",
+ "SLEW": "SLOW"
+ },
+ "bottom_inst.OBUF_11": {
+ "DRIVE": "4",
+ "IOSTANDARD": "LVCMOS25",
+ "IO_LOC_PAIRS": "out_b[1]:R2",
+ "SLEW": "FAST"
+ },
+ "bottom_inst.OBUF_9": {
+ "IOSTANDARD": "DIFF_SSTL135",
+ "IO_LOC_PAIRS": "led[2]:M6",
+ "SLEW": "FAST"
+ },
+ "bottom_intermediate_inst.OBUF_8": {
+ "DRIVE": "16",
+ "IOSTANDARD": "SSTL135",
+ "IO_LOC_PAIRS": "led[3]:N4",
+ "SLEW": "SLOW"
+ }
+}
\ No newline at end of file
diff --git a/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl
new file mode 100644
index 0000000..7303563
--- /dev/null
+++ b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl
@@ -0,0 +1,15 @@
+yosys -import
+if { [info procs get_ports] == {} } { plugin -i design_introspection }
+if { [info procs read_xdc] == {} } { plugin -i xdc }
+yosys -import ;# ingest plugin commands
+
+read_verilog $::env(DESIGN_TOP).v
+# -flatten is used to ensure that the output eblif has only one module.
+# Some of symbiflow expects eblifs with only one module.
+synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
+
+#Read the design constraints
+read_xdc -part_json [file dirname [info script]]/../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
+
+# Write the design in JSON format.
+write_json [test_output_path "package_pins-dict-space.json"]
diff --git a/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.v b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.v
new file mode 100644
index 0000000..d4d172d
--- /dev/null
+++ b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.v
@@ -0,0 +1,111 @@
+// Copyright (C) 2020-2021 The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+
+module top (
+ input clk,
+ output [3:0] led,
+ inout out_a,
+ output [1:0] out_b,
+ output signal_p,
+ output signal_n
+);
+
+ wire LD6, LD7, LD8, LD9;
+ wire inter_wire, inter_wire_2;
+ localparam BITS = 1;
+ localparam LOG2DELAY = 25;
+
+ reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+ always @(posedge clk) begin
+ counter <= counter + 1;
+ end
+ assign led[1] = inter_wire;
+ assign inter_wire = inter_wire_2;
+ assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
+ OBUFTDS OBUFTDS_2 (
+ .I (LD6),
+ .O (signal_p),
+ .OB(signal_n),
+ .T (1'b1)
+ );
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_6 (
+ .I(LD6),
+ .O(led[0])
+ );
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_7 (
+ .I(LD7),
+ .O(inter_wire_2)
+ );
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_OUT (
+ .I(LD7),
+ .O(out_a)
+ );
+ bottom bottom_inst (
+ .I (LD8),
+ .O (led[2]),
+ .OB(out_b)
+ );
+ bottom_intermediate bottom_intermediate_inst (
+ .I(LD9),
+ .O(led[3])
+ );
+endmodule
+
+module bottom_intermediate (
+ input I,
+ output O
+);
+ wire bottom_intermediate_wire;
+ assign O = bottom_intermediate_wire;
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_8 (
+ .I(I),
+ .O(bottom_intermediate_wire)
+ );
+endmodule
+
+module bottom (
+ input I,
+ output [1:0] OB,
+ output O
+);
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_9 (
+ .I(I),
+ .O(O)
+ );
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_10 (
+ .I(I),
+ .O(OB[0])
+ );
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_11 (
+ .I(I),
+ .O(OB[1])
+ );
+endmodule
+
diff --git a/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.xdc b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.xdc
new file mode 100644
index 0000000..70453d1
--- /dev/null
+++ b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.xdc
@@ -0,0 +1,29 @@
+#OBUF_6
+set_property PACKAGE_PIN D10 [get_ports {led[0]}]
+set_property DRIVE 12 [get_ports {led[0]}]
+#OBUF_7
+set_property -dict { PACKAGE_PIN A9 IOSTANDARD SSTL135 } [get_ports {led[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports led[1]]
+set_property SLEW FAST [get_ports led[1]]
+#OBUF_OUT
+set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports out_a]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports out_a]
+set_property SLEW FAST [get_ports out_a]
+#bottom_inst.OBUF_10
+set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18} [get_ports {out_b[0]}]
+set_property SLEW SLOW [get_ports {out_b[0]}]
+#bottom_inst.OBUF_11
+set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS25 } [get_ports {out_b[1]}]
+set_property DRIVE 4 [get_ports {out_b[1]}]
+set_property SLEW FAST [get_ports {out_b[1]}]
+#bottom_inst.OBUF_9
+set_property -dict {PACKAGE_PIN M6 IOSTANDARD DIFF_SSTL135} [get_ports {led[2]}]
+set_property SLEW FAST [get_ports {led[2]}]
+#bottom_intermediate_inst.OBUF_8
+set_property -dict {PACKAGE_PIN N4 IOSTANDARD SSTL135} [get_ports {led[3]}]
+set_property DRIVE 16 [get_ports {led[3]}]
+#OBUFTDS_2
+set_property -dict {PACKAGE_PIN N2 IOSTANDARD DIFF_SSTL135} [get_ports signal_p]
+set_property PACKAGE_PIN N1 [get_ports signal_n]
+set_property SLEW FAST [get_ports signal_p]
+
diff --git a/xdc-plugin/xdc.cc b/xdc-plugin/xdc.cc
index 2e935ea..387d191 100644
--- a/xdc-plugin/xdc.cc
+++ b/xdc-plugin/xdc.cc
@@ -136,7 +136,9 @@
std::vector<std::string> tokens;
std::string intermediate;
while (getline(args_stream, intermediate, ' ')) {
- tokens.push_back(intermediate);
+ if (intermediate != "\0") {
+ tokens.push_back(intermediate);
+ }
}
if (tokens.size() % 2 != 0) {
log_cmd_error("Invalid number of dict parameters: %lu.\n", tokens.size());
