)]}'
{
  "commit": "d849fd446dc3510abc93d8f65313e6ad09440a4f",
  "tree": "c9977a3b63e1fad99df9c5f68d9f9a6b9ecd53c7",
  "parents": [
    "fb94f804e008fb00103b120ed6d755e3836408b7",
    "47c71ac99e57be8f92184b0941e5b96b4bca7cc3"
  ],
  "author": {
    "name": "Tomasz Gorochowik",
    "email": "tgorochowik@antmicro.com",
    "time": "Wed Mar 16 17:13:13 2022 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Mar 16 17:13:13 2022 +0100"
  },
  "message": "Merge pull request #272 from antmicro/verilog-via-uhdm-force-parse\n\nForce -parse flag for Surelog when reading Verilog directly",
  "tree_diff": []
}