diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index 86292f5..718241c 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -1,5 +1,6 @@
 # counter, counter2, pll - test buffer and clock divider propagation
 # set_false_path - test the set_false_path command
+# set_max_delay - test the set_max_delay command
 
 TESTS = counter \
 	counter2 \
@@ -7,7 +8,8 @@
 	pll_div \
 	pll_fbout_phase \
 	pll_approx_equal \
-	set_false_path
+	set_false_path \
+	set_max_delay
 
 .PHONY: $(TESTS)
 
@@ -18,6 +20,7 @@
 pll_fbout_phase_verify = $(call compare,pll_fbout_phase,sdc)
 pll_approx_equal_verify = $(call compare,pll_approx_equal,sdc)
 set_false_path_verify = $(call compare,set_false_path,sdc)
+set_max_delay_verify = $(call compare,set_max_delay,sdc)
 
 all: $(TESTS)
 compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.golden.sdc b/sdc-plugin/tests/set_max_delay/set_max_delay.golden.sdc
new file mode 100644
index 0000000..02ed95d
--- /dev/null
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.golden.sdc
@@ -0,0 +1,3 @@
+set_max_delay 1 -to inter_wire
+set_max_delay 2 -from clk
+set_max_delay 3 -from clk -to bottom_inst.I
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
new file mode 100644
index 0000000..8cfde6a
--- /dev/null
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
@@ -0,0 +1,19 @@
+yosys -import
+plugin -i sdc
+#Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+read_verilog set_max_delay.v
+# Some of symbiflow expects eblifs with only one module.
+synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+
+# -to inter_wire net
+set_max_delay 1 -to inter_wire
+
+# -from clk net (quiet)
+set_max_delay 2 -quiet -from clk
+
+# -from clk to bottom_inst/I
+set_max_delay 3 -from clk -to bottom_inst.I
+
+write_sdc set_max_delay.sdc
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.v b/sdc-plugin/tests/set_max_delay/set_max_delay.v
new file mode 100644
index 0000000..d40055b
--- /dev/null
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.v
@@ -0,0 +1,75 @@
+module top (
+	(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input  clk,
+	output [3:0] led,
+	inout out_a,
+	output [1:0] out_b,
+	output signal_p,
+	output signal_n
+);
+
+	wire LD6, LD7, LD8, LD9;
+	wire inter_wire, inter_wire_2;
+	localparam BITS = 1;
+	localparam LOG2DELAY = 25;
+
+	reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+	always @(posedge clk) begin
+		counter <= counter + 1;
+	end
+	assign led[1] = inter_wire;
+	assign inter_wire = inter_wire_2;
+	assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
+	OBUFTDS OBUFTDS_2(
+		.I(LD6),
+		.O(signal_p),
+		.OB(signal_n),
+		.T(1'b1)
+	);
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_6(.I(LD6), .O(led[0]));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_7(.I(LD7), .O(inter_wire_2));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_OUT(.I(LD7), .O(out_a));
+	bottom bottom_inst(.I(LD8), .O(led[2]), .OB(out_b));
+	bottom_intermediate bottom_intermediate_inst(.I(LD9), .O(led[3]));
+endmodule
+
+module bottom_intermediate (
+	input I,
+	output O
+);
+	wire bottom_intermediate_wire;
+	assign O = bottom_intermediate_wire;
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_8(.I(I), .O(bottom_intermediate_wire));
+endmodule
+
+module bottom (
+	input I,
+	output [1:0] OB,
+	output O
+);
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_9(.I(I), .O(O));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_10(.I(I), .O(OB[0]));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_11(.I(I), .O(OB[1]));
+endmodule
+