)]}'
{
  "commit": "dc9605ac5240ef96e91bc599a295b5f54a946d20",
  "tree": "c583ddd7ae584733642736dcfe1679843dcf1151",
  "parents": [
    "56f957caa573658015cc4256cd9ebf2a0cc70a19"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Jun 06 07:55:10 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Jun 06 11:47:51 2023 +0200"
  },
  "message": "yosys-systemverilog: fix multirange with dot usage\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "06a50e3d4e2597a907e8b533b97635f4ca7e6fb0",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "64b2203f9724791e4b9840648436b041d17bd0d3",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}