)]}'
{
  "commit": "dd4cf9b3109ee033a63867887c32ed8526a87774",
  "tree": "d99b3cf92fc4937b3679c621d76957bbb766d7b1",
  "parents": [
    "d852e75feff795ce4de9e207ff08055cbc0212c3",
    "e8ad82018d392d3ddf3f4f947e4a1a56e7ff1c0f"
  ],
  "author": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Mon May 15 16:09:41 2023 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon May 15 16:09:41 2023 +0200"
  },
  "message": "Merge pull request #508 from antmicro/mglb/AddSynthArg\n\nsystemverilog-plugin: Enable non-synthesizable code removal in Surelog.",
  "tree_diff": []
}