tree d99b3cf92fc4937b3679c621d76957bbb766d7b1
parent d852e75feff795ce4de9e207ff08055cbc0212c3
parent e8ad82018d392d3ddf3f4f947e4a1a56e7ff1c0f
author Mariusz Glebocki <mglebocki@antmicro.com> 1684159781 +0200
committer GitHub <noreply@github.com> 1684159781 +0200
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Merge pull request #508 from antmicro/mglb/AddSynthArg

systemverilog-plugin: Enable non-synthesizable code removal in Surelog.