)]}'
{
  "commit": "ddd19038cf215eb5c1e3858fd82564d0aa825bf8",
  "tree": "711ec699b45195b1729af62a38adb54e9c4105a7",
  "parents": [
    "d491817fe2fce9b851959caf831ddaa96bb5074d"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Thu Mar 23 12:57:34 2023 +0100"
  },
  "committer": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Wed Apr 05 15:51:50 2023 +0200"
  },
  "message": "systemverilog-plugin: Adjusting simplify.cc, removing unneded code\n\nSigned-off-by: Magdalena Andrys \u003cmandrys@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "78e5768efe90469f7297c6d7de33ffa7fa7b98a6",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/third_party/yosys/simplify.cc",
      "new_id": "71d15a4d0b6d0ae3bc816d5abdb8517898406d9f",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/third_party/yosys/simplify.cc"
    }
  ]
}