)]}'
{
  "commit": "e0a923cc0bf6b2149994857ba47dc71c5791f227",
  "tree": "d7a860077d22f2090bb23304222e0bd6c143753d",
  "parents": [
    "24755e3b43400ad25e90fe01cc764a28a12de999",
    "0c7f1c025a026b29d86642936f9e57415cc24f31"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 13 17:04:06 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Mar 13 17:04:06 2023 +0100"
  },
  "message": "Merge pull request #466 from antmicro/kr/process_module\n\nsystemverilog-plugin: update module parameters processing",
  "tree_diff": []
}