tree d7a860077d22f2090bb23304222e0bd6c143753d
parent 24755e3b43400ad25e90fe01cc764a28a12de999
parent 0c7f1c025a026b29d86642936f9e57415cc24f31
author Kamil Rakoczy <krakoczy@antmicro.com> 1678723446 +0100
committer GitHub <noreply@github.com> 1678723446 +0100
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Merge pull request #466 from antmicro/kr/process_module

systemverilog-plugin: update module parameters processing