Merge pull request #128 from antmicro/add-new-write-edif-backend
ql: add custom edif backend
diff --git a/ql-qlf-plugin/Makefile b/ql-qlf-plugin/Makefile
index 9886c83..e2fa3e1 100644
--- a/ql-qlf-plugin/Makefile
+++ b/ql-qlf-plugin/Makefile
@@ -16,44 +16,44 @@
include ../Makefile_plugin.common
COMMON = common
-QLF_K4N8_DIR = ql-qlf-k4n8
-QLF_K6N10_DIR = ql-qlf-k6n10
+QLF_K4N8_DIR = qlf_k4n8
+QLF_K6N10_DIR = qlf_k6n10
PP3_DIR = pp3
-VERILOG_MODULES = $(COMMON)/cells_sim.v \
- $(QLF_K4N8_DIR)/qlf_k4n8_arith_map.v \
- $(QLF_K4N8_DIR)/qlf_k4n8_cells_sim.v \
- $(QLF_K4N8_DIR)/qlf_k4n8_ffs_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_arith_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_brams_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_brams.txt \
- $(QLF_K6N10_DIR)/qlf_k6n10_cells_sim.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_ffs_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_dsp_map.v \
- $(QLF_K6N10_DIR)/qlf_k6n10_lut_map.v \
- $(PP3_DIR)/pp3_abc9_map.v \
- $(PP3_DIR)/pp3_abc9_model.v \
- $(PP3_DIR)/pp3_abc9_unmap.v \
- $(PP3_DIR)/pp3_cells_map.v \
- $(PP3_DIR)/pp3_cells_sim.v \
- $(PP3_DIR)/pp3_ffs_map.v \
- $(PP3_DIR)/pp3_latches_map.v \
- $(PP3_DIR)/pp3_lut_map.v \
- $(PP3_DIR)/pp3_lutdefs.txt \
- $(PP3_DIR)/pp3_brams_sim.v \
- $(PP3_DIR)/pp3_brams_map.v \
- $(PP3_DIR)/pp3_brams.txt \
- $(PP3_DIR)/pp3_bram_init_8_16.vh \
- $(PP3_DIR)/pp3_bram_init_32.vh \
- $(PP3_DIR)/pp3_qlal4s3b_sim.v \
- $(PP3_DIR)/pp3_mult_sim.v \
- $(PP3_DIR)/pp3_qlal3_sim.v \
+VERILOG_MODULES = $(COMMON)/cells_sim.v \
+ $(QLF_K4N8_DIR)/arith_map.v \
+ $(QLF_K4N8_DIR)/cells_sim.v \
+ $(QLF_K4N8_DIR)/ffs_map.v \
+ $(QLF_K6N10_DIR)/arith_map.v \
+ $(QLF_K6N10_DIR)/brams_map.v \
+ $(QLF_K6N10_DIR)/brams.txt \
+ $(QLF_K6N10_DIR)/cells_sim.v \
+ $(QLF_K6N10_DIR)/ffs_map.v \
+ $(QLF_K6N10_DIR)/dsp_map.v \
+ $(QLF_K6N10_DIR)/lut_map.v \
+ $(PP3_DIR)/abc9_map.v \
+ $(PP3_DIR)/abc9_model.v \
+ $(PP3_DIR)/abc9_unmap.v \
+ $(PP3_DIR)/cells_map.v \
+ $(PP3_DIR)/cells_sim.v \
+ $(PP3_DIR)/ffs_map.v \
+ $(PP3_DIR)/latches_map.v \
+ $(PP3_DIR)/lut_map.v \
+ $(PP3_DIR)/lutdefs.txt \
+ $(PP3_DIR)/brams_sim.v \
+ $(PP3_DIR)/brams_map.v \
+ $(PP3_DIR)/brams.txt \
+ $(PP3_DIR)/bram_init_8_16.vh \
+ $(PP3_DIR)/bram_init_32.vh \
+ $(PP3_DIR)/qlal4s3b_sim.v \
+ $(PP3_DIR)/mult_sim.v \
+ $(PP3_DIR)/qlal3_sim.v \
retrieve-pmgen:=$(shell mkdir -p pmgen && wget -nc -O pmgen/pmgen.py https://raw.githubusercontent.com/SymbiFlow/yosys/master%2Bwip/passes/pmgen/pmgen.py)
pre-build:=$(shell python3 pmgen/pmgen.py -o pmgen/ql-dsp-pm.h -p ql_dsp ql_dsp.pmg)
install_modules: $(VERILOG_MODULES)
- $(foreach f,$^,install -D $(f) $(DATA_DIR)/quicklogic/$(notdir $(f));)
+ $(foreach f,$^,install -D $(f) $(DATA_DIR)/quicklogic/$(f);)
install: install_modules
diff --git a/ql-qlf-plugin/pp3/pp3_abc9_map.v b/ql-qlf-plugin/pp3/abc9_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_abc9_map.v
rename to ql-qlf-plugin/pp3/abc9_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_abc9_model.v b/ql-qlf-plugin/pp3/abc9_model.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_abc9_model.v
rename to ql-qlf-plugin/pp3/abc9_model.v
diff --git a/ql-qlf-plugin/pp3/pp3_abc9_unmap.v b/ql-qlf-plugin/pp3/abc9_unmap.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_abc9_unmap.v
rename to ql-qlf-plugin/pp3/abc9_unmap.v
diff --git a/ql-qlf-plugin/pp3/pp3_bram_init_32.vh b/ql-qlf-plugin/pp3/bram_init_32.vh
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_bram_init_32.vh
rename to ql-qlf-plugin/pp3/bram_init_32.vh
diff --git a/ql-qlf-plugin/pp3/pp3_bram_init_8_16.vh b/ql-qlf-plugin/pp3/bram_init_8_16.vh
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_bram_init_8_16.vh
rename to ql-qlf-plugin/pp3/bram_init_8_16.vh
diff --git a/ql-qlf-plugin/pp3/pp3_brams.txt b/ql-qlf-plugin/pp3/brams.txt
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_brams.txt
rename to ql-qlf-plugin/pp3/brams.txt
diff --git a/ql-qlf-plugin/pp3/pp3_brams_map.v b/ql-qlf-plugin/pp3/brams_map.v
similarity index 99%
rename from ql-qlf-plugin/pp3/pp3_brams_map.v
rename to ql-qlf-plugin/pp3/brams_map.v
index 7e34cd3..1941a3d 100644
--- a/ql-qlf-plugin/pp3/pp3_brams_map.v
+++ b/ql-qlf-plugin/pp3/brams_map.v
@@ -71,7 +71,7 @@
generate
if (CFG_DBITS <= 16) begin
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_32.vh"
+ `include "bram_init_32.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR),
.A1_1(GND),
@@ -138,7 +138,7 @@
);
end else if (CFG_DBITS <= 32) begin
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_32.vh"
+ `include "bram_init_32.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR),
.A1_1(GND),
@@ -287,7 +287,7 @@
end
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_8_16.vh"
+ `include "bram_init_8_16.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR_11),
.A1_1(GND),
diff --git a/ql-qlf-plugin/pp3/pp3_brams_sim.v b/ql-qlf-plugin/pp3/brams_sim.v
similarity index 99%
rename from ql-qlf-plugin/pp3/pp3_brams_sim.v
rename to ql-qlf-plugin/pp3/brams_sim.v
index 4d1822a..2795852 100644
--- a/ql-qlf-plugin/pp3/pp3_brams_sim.v
+++ b/ql-qlf-plugin/pp3/brams_sim.v
@@ -2129,7 +2129,7 @@
endgenerate
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_8_16.vh"
+ `include "bram_init_8_16.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
@@ -2332,7 +2332,7 @@
if (data_width_int <= 16) begin
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_8_16.vh"
+ `include "bram_init_8_16.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
@@ -2409,7 +2409,7 @@
end else if (data_width_int > 16) begin
ram8k_2x1_cell_macro #(
- `include "pp3_bram_init_32.vh"
+ `include "bram_init_32.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
diff --git a/ql-qlf-plugin/pp3/pp3_cells_map.v b/ql-qlf-plugin/pp3/cells_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_cells_map.v
rename to ql-qlf-plugin/pp3/cells_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_cells_sim.v b/ql-qlf-plugin/pp3/cells_sim.v
similarity index 98%
rename from ql-qlf-plugin/pp3/pp3_cells_sim.v
rename to ql-qlf-plugin/pp3/cells_sim.v
index abf6e3a..e498d4e 100644
--- a/ql-qlf-plugin/pp3/pp3_cells_sim.v
+++ b/ql-qlf-plugin/pp3/cells_sim.v
@@ -479,11 +479,11 @@
endmodule
// Include simulation models of QLAL4S3B eFPGA interface
-`include "pp3_qlal4s3b_sim.v"
+`include "qlal4s3b_sim.v"
// Include simulation models for QLAL3 hard blocks
-`include "pp3_qlal3_sim.v"
+`include "qlal3_sim.v"
// Include BRAM and FIFO simulation models
-`include "pp3_brams_sim.v"
+`include "brams_sim.v"
// Include MULT simulation models
-`include "pp3_mult_sim.v"
+`include "mult_sim.v"
diff --git a/ql-qlf-plugin/pp3/pp3_ffs_map.v b/ql-qlf-plugin/pp3/ffs_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_ffs_map.v
rename to ql-qlf-plugin/pp3/ffs_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_latches_map.v b/ql-qlf-plugin/pp3/latches_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_latches_map.v
rename to ql-qlf-plugin/pp3/latches_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_lut_map.v b/ql-qlf-plugin/pp3/lut_map.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_lut_map.v
rename to ql-qlf-plugin/pp3/lut_map.v
diff --git a/ql-qlf-plugin/pp3/pp3_lutdefs.txt b/ql-qlf-plugin/pp3/lutdefs.txt
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_lutdefs.txt
rename to ql-qlf-plugin/pp3/lutdefs.txt
diff --git a/ql-qlf-plugin/pp3/pp3_mult_sim.v b/ql-qlf-plugin/pp3/mult_sim.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_mult_sim.v
rename to ql-qlf-plugin/pp3/mult_sim.v
diff --git a/ql-qlf-plugin/pp3/pp3_qlal3_sim.v b/ql-qlf-plugin/pp3/qlal3_sim.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_qlal3_sim.v
rename to ql-qlf-plugin/pp3/qlal3_sim.v
diff --git a/ql-qlf-plugin/pp3/pp3_qlal4s3b_sim.v b/ql-qlf-plugin/pp3/qlal4s3b_sim.v
similarity index 100%
rename from ql-qlf-plugin/pp3/pp3_qlal4s3b_sim.v
rename to ql-qlf-plugin/pp3/qlal4s3b_sim.v
diff --git a/ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_arith_map.v b/ql-qlf-plugin/qlf_k4n8/arith_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_arith_map.v
rename to ql-qlf-plugin/qlf_k4n8/arith_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_cells_sim.v b/ql-qlf-plugin/qlf_k4n8/cells_sim.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_cells_sim.v
rename to ql-qlf-plugin/qlf_k4n8/cells_sim.v
diff --git a/ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_ffs_map.v b/ql-qlf-plugin/qlf_k4n8/ffs_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k4n8/qlf_k4n8_ffs_map.v
rename to ql-qlf-plugin/qlf_k4n8/ffs_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_arith_map.v b/ql-qlf-plugin/qlf_k6n10/arith_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_arith_map.v
rename to ql-qlf-plugin/qlf_k6n10/arith_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_brams.txt b/ql-qlf-plugin/qlf_k6n10/brams.txt
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_brams.txt
rename to ql-qlf-plugin/qlf_k6n10/brams.txt
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_brams_map.v b/ql-qlf-plugin/qlf_k6n10/brams_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_brams_map.v
rename to ql-qlf-plugin/qlf_k6n10/brams_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_cells_sim.v b/ql-qlf-plugin/qlf_k6n10/cells_sim.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_cells_sim.v
rename to ql-qlf-plugin/qlf_k6n10/cells_sim.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_dsp_map.v b/ql-qlf-plugin/qlf_k6n10/dsp_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_dsp_map.v
rename to ql-qlf-plugin/qlf_k6n10/dsp_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_ffs_map.v b/ql-qlf-plugin/qlf_k6n10/ffs_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_ffs_map.v
rename to ql-qlf-plugin/qlf_k6n10/ffs_map.v
diff --git a/ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_lut_map.v b/ql-qlf-plugin/qlf_k6n10/lut_map.v
similarity index 100%
rename from ql-qlf-plugin/ql-qlf-k6n10/qlf_k6n10_lut_map.v
rename to ql-qlf-plugin/qlf_k6n10/lut_map.v
diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 4a9abc5..36c3afe 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -190,9 +190,9 @@
{
if (check_label("begin")) {
std::string readVelArgs;
- readVelArgs = " +/quicklogic/" + family + "_cells_sim.v";
+ readVelArgs = " +/quicklogic/" + family + "/cells_sim.v";
- run("read_verilog -lib -specify +/quicklogic/cells_sim.v" + readVelArgs);
+ run("read_verilog -lib -specify +/quicklogic/common/cells_sim.v" + readVelArgs);
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
@@ -221,7 +221,7 @@
run("memory_dff");
run("wreduce t:$mul");
run("techmap -map +/mul2dsp.v -map +/quicklogic/" + family +
- "_dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
+ "/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
"-D DSP_NAME=$__MUL16X16",
"(if -no_dsp)");
@@ -245,11 +245,11 @@
}
if (check_label("map_bram", "(skip if -no_bram)") && (family == "qlf_k6n10" || family == "pp3") && inferBram) {
- run("memory_bram -rules +/quicklogic/" + family + "_brams.txt");
+ run("memory_bram -rules +/quicklogic/" + family + "/brams.txt");
if (family == "pp3") {
run("pp3_braminit");
}
- run("techmap -map +/quicklogic/" + family + "_brams_map.v");
+ run("techmap -map +/quicklogic/" + family + "/brams_map.v");
}
if (check_label("map_ffram")) {
@@ -262,7 +262,7 @@
if (check_label("map_gates")) {
if (inferAdder && (family == "qlf_k4n8" || family == "qlf_k6n10")) {
- run("techmap -map +/techmap.v -map +/quicklogic/" + family + "_arith_map.v");
+ run("techmap -map +/techmap.v -map +/quicklogic/" + family + "/arith_map.v");
} else {
run("techmap");
}
@@ -289,9 +289,9 @@
// $_DLATCH_SRPPP_ 0");
} else if (family == "pp3") {
run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
- run("techmap -map +/quicklogic/" + family + "_cells_map.v");
+ run("techmap -map +/quicklogic/" + family + "/cells_map.v");
}
- std::string techMapArgs = " -map +/techmap.v -map +/quicklogic/" + family + "_ffs_map.v";
+ std::string techMapArgs = " -map +/techmap.v -map +/quicklogic/" + family + "/ffs_map.v";
if (!noffmap) {
run("techmap " + techMapArgs);
}
@@ -310,14 +310,14 @@
} else if (family == "qlf_k4n8") {
run("abc -lut 4 ");
} else if (family == "pp3") {
- run("techmap -map +/quicklogic/" + family + "_latches_map.v");
+ run("techmap -map +/quicklogic/" + family + "/latches_map.v");
if (abc9) {
- run("read_verilog -lib -specify -icells +/quicklogic/" + family + "_abc9_model.v");
- run("techmap -map +/quicklogic/" + family + "_abc9_map.v");
+ run("read_verilog -lib -specify -icells +/quicklogic/" + family + "/abc9_model.v");
+ run("techmap -map +/quicklogic/" + family + "/abc9_map.v");
run("abc9 -maxlut 4 -dff");
- run("techmap -map +/quicklogic/" + family + "_abc9_unmap.v");
+ run("techmap -map +/quicklogic/" + family + "/abc9_unmap.v");
} else {
- std::string lutDefs = "+/quicklogic/" + family + "_lutdefs.txt";
+ std::string lutDefs = "+/quicklogic/" + family + "/lutdefs.txt";
rewrite_filename(lutDefs);
std::string abcArgs = "+read_lut," + lutDefs +
@@ -336,7 +336,7 @@
if (check_label("map_cells") && (family == "qlf_k6n10" || family == "pp3")) {
std::string techMapArgs;
- techMapArgs = "-map +/quicklogic/" + family + "_lut_map.v";
+ techMapArgs = "-map +/quicklogic/" + family + "/lut_map.v";
run("techmap " + techMapArgs);
run("clean");
}
diff --git a/ql-qlf-plugin/tests/dffs/dffs.tcl b/ql-qlf-plugin/tests/dffs/dffs.tcl
index 9b1941c..d96b3e6 100644
--- a/ql-qlf-plugin/tests/dffs/dffs.tcl
+++ b/ql-qlf-plugin/tests/dffs/dffs.tcl
@@ -8,7 +8,7 @@
# DFF
hierarchy -top my_dff
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8 -top my_dff
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8 -top my_dff
design -load postopt
yosys cd my_dff
stat
@@ -163,7 +163,7 @@
# DFF
hierarchy -top my_dff
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top my_dff
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top my_dff
design -load postopt
yosys cd my_dff
stat
@@ -412,7 +412,7 @@
# DFF
hierarchy -top my_dff
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dff
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dff
design -load postopt
yosys cd my_dff
stat
@@ -427,7 +427,7 @@
design -load read
hierarchy -top my_dffe
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffe
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffe
design -load postopt
yosys cd my_dffe
stat
@@ -441,7 +441,7 @@
design -load read
hierarchy -top my_dffr_p
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffr_p
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffr_p
design -load postopt
yosys cd my_dffr_p
stat
@@ -458,7 +458,7 @@
design -load read
hierarchy -top my_dffr_n
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffr_n
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffr_n
design -load postopt
yosys cd my_dffr_n
stat
@@ -476,7 +476,7 @@
design -load read
hierarchy -top my_dffs_clk_p
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffs_clk_p
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffs_clk_p
design -load postopt
yosys cd my_dffs_clk_p
stat
@@ -494,7 +494,7 @@
design -load read
hierarchy -top my_dffs_clk_n
yosys proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 -top my_dffs_clk_n
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffs_clk_n
design -load postopt
yosys cd my_dffs_clk_n
stat
diff --git a/ql-qlf-plugin/tests/fsm/fsm.tcl b/ql-qlf-plugin/tests/fsm/fsm.tcl
index d6d72e2..2e09677 100644
--- a/ql-qlf-plugin/tests/fsm/fsm.tcl
+++ b/ql-qlf-plugin/tests/fsm/fsm.tcl
@@ -9,7 +9,7 @@
yosys proc
flatten
-equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -run :prove -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
async2sync
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
diff --git a/ql-qlf-plugin/tests/full_adder/full_adder.tcl b/ql-qlf-plugin/tests/full_adder/full_adder.tcl
index 3093086..6365284 100644
--- a/ql-qlf-plugin/tests/full_adder/full_adder.tcl
+++ b/ql-qlf-plugin/tests/full_adder/full_adder.tcl
@@ -6,7 +6,7 @@
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top full_adder
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8
design -reset
@@ -14,14 +14,14 @@
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top subtractor
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8
design -reset
# Equivalence check for adder synthesis for qlf-k6n10
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top full_adder
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10
design -reset
@@ -31,7 +31,7 @@
#read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
#hierarchy -check -top subtractor
#yosys proc
-#equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10
+#equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10
design -reset
@@ -39,7 +39,7 @@
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top full_adder
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd full_adder
@@ -58,7 +58,7 @@
read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v
hierarchy -check -top subtractor
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd subtractor
diff --git a/ql-qlf-plugin/tests/logic/logic.tcl b/ql-qlf-plugin/tests/logic/logic.tcl
index 6bfb7cb..0e10db5 100644
--- a/ql-qlf-plugin/tests/logic/logic.tcl
+++ b/ql-qlf-plugin/tests/logic/logic.tcl
@@ -6,7 +6,7 @@
read_verilog $::env(DESIGN_TOP).v
hierarchy -top top
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8
design -load postopt
yosys cd top
@@ -19,7 +19,7 @@
read_verilog $::env(DESIGN_TOP).v
hierarchy -top top
yosys proc
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10
design -load postopt
yosys cd top
@@ -32,7 +32,7 @@
read_verilog $::env(DESIGN_TOP).v
hierarchy -top top
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd top
diff --git a/ql-qlf-plugin/tests/logic/logic.ys b/ql-qlf-plugin/tests/logic/logic.ys
index c7f0cd5..037896c 100644
--- a/ql-qlf-plugin/tests/logic/logic.ys
+++ b/ql-qlf-plugin/tests/logic/logic.ys
@@ -2,7 +2,7 @@
read_verilog ./logic.v
hierarchy -top top
proc
-equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic -family qlf_k4n8
+equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8
design -load postopt
cd top
diff --git a/ql-qlf-plugin/tests/mux/mux.tcl b/ql-qlf-plugin/tests/mux/mux.tcl
index 260e242..47a1e1b 100644
--- a/ql-qlf-plugin/tests/mux/mux.tcl
+++ b/ql-qlf-plugin/tests/mux/mux.tcl
@@ -7,7 +7,7 @@
hierarchy -top mux2
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd mux2
select -assert-count 1 t:LUT3
@@ -19,7 +19,7 @@
design -load read
hierarchy -top mux4
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd mux4
select -assert-count 3 t:LUT3
@@ -31,7 +31,7 @@
design -load read
hierarchy -top mux8
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd mux8
select -assert-count 1 t:LUT1
@@ -45,7 +45,7 @@
design -load read
hierarchy -top mux16
yosys proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3
design -load postopt
yosys cd mux16
select -assert-count 1 t:LUT3
diff --git a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys
index 5539004..20228ca 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys
+++ b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys
@@ -8,7 +8,7 @@
hierarchy -top BRAM_32x512
proc
memory
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_32x512
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_32x512
design -load postopt
cd BRAM_32x512
stat
@@ -19,7 +19,7 @@
hierarchy -top BRAM_32x512
proc
memory
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_16x1024
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_16x1024
design -load postopt
cd BRAM_16x1024
stat
@@ -30,7 +30,7 @@
hierarchy -top BRAM_8x2048
proc
memory
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_8x2048
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_8x2048
design -load postopt
cd BRAM_8x2048
stat
@@ -41,7 +41,7 @@
hierarchy -top BRAM_4x4096
proc
memory
-equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_4x4096
+equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_4x4096
design -load postopt
cd BRAM_4x4096
stat
diff --git a/ql-qlf-plugin/tests/tribuf/tribuf.tcl b/ql-qlf-plugin/tests/tribuf/tribuf.tcl
index 067e7fd..acee086 100644
--- a/ql-qlf-plugin/tests/tribuf/tribuf.tcl
+++ b/ql-qlf-plugin/tests/tribuf/tribuf.tcl
@@ -9,7 +9,7 @@
tribuf
flatten
synth
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/simcells.v synth_quicklogic -family pp3
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/simcells.v synth_quicklogic -family pp3
design -load postopt
yosys cd tristate
select -assert-count 2 t:inpad
