diff --git a/ql-qlf-plugin/ql-dsp-io-regs.cc b/ql-qlf-plugin/ql-dsp-io-regs.cc
index 5772513..3ea2a12 100644
--- a/ql-qlf-plugin/ql-dsp-io-regs.cc
+++ b/ql-qlf-plugin/ql-dsp-io-regs.cc
@@ -82,6 +82,15 @@
             std::string cell_type = cell.second->type.str();
             if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) {
                 auto dsp = cell.second;
+
+                // If the cell does not have the "is_inferred" attribute set
+                // then don't touch it.
+                if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) ||
+                     dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false)
+                {
+                    continue;
+                }
+
                 bool del_clk = true;
                 bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3"));
 
diff --git a/ql-qlf-plugin/ql-dsp-macc.cc b/ql-qlf-plugin/ql-dsp-macc.cc
index 7f865b5..4fdfff1 100644
--- a/ql-qlf-plugin/ql-dsp-macc.cc
+++ b/ql-qlf-plugin/ql-dsp-macc.cc
@@ -131,6 +131,9 @@
     // Add the DSP cell
     RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type);
 
+    // Set attributes
+    cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true);
+
     // Get input/output data signals
     RTLIL::SigSpec sig_a;
     RTLIL::SigSpec sig_b;
diff --git a/ql-qlf-plugin/ql-dsp-simd.cc b/ql-qlf-plugin/ql-dsp-simd.cc
index b2935a9..dfa3e38 100644
--- a/ql-qlf-plugin/ql-dsp-simd.cc
+++ b/ql-qlf-plugin/ql-dsp-simd.cc
@@ -261,6 +261,16 @@
                     simd->setParam(RTLIL::escape_id("MODE_BITS"), RTLIL::Const(mode_bits));
                     log_assert(mode_bits.size() == mode_bits_size);
 
+                    // Handle the "is_inferred" attribute. If one of the fragments
+                    // is not inferred mark the whole DSP as not inferred
+                    bool is_inferred_a = dsp_a->has_attribute(RTLIL::escape_id("is_inferred")) ?
+                        dsp_a->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false;
+                    bool is_inferred_b = dsp_b->has_attribute(RTLIL::escape_id("is_inferred")) ?
+                        dsp_b->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false;
+
+                    simd->set_bool_attribute(RTLIL::escape_id("is_inferred"),
+                        is_inferred_a && is_inferred_b);
+
                     // Mark DSP parts for removal
                     cellsToRemove.push_back(dsp_a);
                     cellsToRemove.push_back(dsp_b);
diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_map.v b/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
index bbfc494..bb9f052 100644
--- a/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
@@ -34,6 +34,7 @@
                             {{(18 - B_WIDTH){1'b0}},         B};
 
     generate if (`USE_DSP_CFG_PARAMS == 0) begin
+        (* is_inferred=1 *)
         dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ (
             .a_i                (a),
             .b_i                (b),
@@ -53,6 +54,7 @@
             .register_inputs_i  (1'b0)
         );
     end else begin
+        (* is_inferred=1 *)
         dsp_t1_20x18x64_cfg_params #(
             .OUTPUT_SELECT      (3'd0),
             .SATURATE_ENABLE    (1'b0),
@@ -98,6 +100,7 @@
                             {{( 9 - B_WIDTH){1'b0}},         B};
 
     generate if (`USE_DSP_CFG_PARAMS == 0) begin
+        (* is_inferred=1 *)
         dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ (
             .a_i                (a),
             .b_i                (b),
@@ -117,6 +120,7 @@
             .register_inputs_i  (1'b0)
         );
     end else begin
+        (* is_inferred=1 *)
         dsp_t1_10x9x32_cfg_params #(
             .OUTPUT_SELECT      (3'd0),
             .SATURATE_ENABLE    (1'b0),