Merge pull request #67 from antmicro/get_ports_trim_name

get_ports: Trim port name
diff --git a/bank_tiles.h b/common/bank_tiles.h
similarity index 100%
rename from bank_tiles.h
rename to common/bank_tiles.h
diff --git a/common/utils.h b/common/utils.h
new file mode 100644
index 0000000..42ad7b1
--- /dev/null
+++ b/common/utils.h
@@ -0,0 +1,19 @@
+#include <algorithm>
+#include <cctype>
+#include <locale>
+
+inline void trim_left(std::string &str)
+{
+    str.erase(str.begin(), std::find_if(str.begin(), str.end(), [](unsigned char ch) { return !std::isspace(ch); }));
+}
+
+inline void trim_right(std::string &str)
+{
+    str.erase(std::find_if(str.rbegin(), str.rend(), [](unsigned char ch) { return !std::isspace(ch); }).base(), str.end());
+}
+
+inline void trim(std::string &str)
+{
+    trim_left(str);
+    trim_right(str);
+}
diff --git a/design_introspection-plugin/get_ports.cc b/design_introspection-plugin/get_ports.cc
index 042ada7..d6a0916 100644
--- a/design_introspection-plugin/get_ports.cc
+++ b/design_introspection-plugin/get_ports.cc
@@ -18,6 +18,7 @@
  *
  */
 #include "get_ports.h"
+#include "../common/utils.h"
 
 USING_YOSYS_NAMESPACE
 
@@ -30,6 +31,7 @@
 GetPorts::SelectionObjects GetPorts::ExtractSelection(RTLIL::Design *design, const CommandArgs &args)
 {
     std::string port_name = args.selection_objects.at(0);
+    trim(port_name);
     std::string port_str(port_name.size(), '\0');
     int bit(0);
     if (!sscanf(port_name.c_str(), "%[^[][%d]", &port_str[0], &bit)) {
diff --git a/design_introspection-plugin/tests/Makefile b/design_introspection-plugin/tests/Makefile
index fcca1e9..1602a48 100644
--- a/design_introspection-plugin/tests/Makefile
+++ b/design_introspection-plugin/tests/Makefile
@@ -3,6 +3,8 @@
 	get_cells \
 	get_pins
 
+UNIT_TESTS = trim_name
+
 include $(shell pwd)/../../Makefile_test.common
 
 get_nets_verify = $(call diff_test,get_nets,txt)
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.golden.txt b/design_introspection-plugin/tests/get_ports/get_ports.golden.txt
index d87ba55..d427ccd 100644
--- a/design_introspection-plugin/tests/get_ports/get_ports.golden.txt
+++ b/design_introspection-plugin/tests/get_ports/get_ports.golden.txt
@@ -4,3 +4,5 @@
 clk
 led[0] port
 led[0]
+led[1] port
+led[1]
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.tcl b/design_introspection-plugin/tests/get_ports/get_ports.tcl
index eca245d..f82305a 100644
--- a/design_introspection-plugin/tests/get_ports/get_ports.tcl
+++ b/design_introspection-plugin/tests/get_ports/get_ports.tcl
@@ -10,18 +10,24 @@
 
 set fp [open "get_ports.txt" "w"]
 
-puts "\nsignal_p port"
+puts "\n signal_p port"
 puts $fp "signal_p port"
 puts $fp [get_ports signal_p]
 
-puts "\nclk port"
+puts "\n clk port"
 puts $fp "clk port"
 puts $fp [get_ports clk]
 
-puts {\nled[0] port}
+puts "\n"
+puts { led[0] port}
 puts $fp {led[0] port}
 puts $fp [get_ports {led[0]}]
 
+puts "\n"
+puts { led[1] port}
+puts $fp {led[1] port}
+puts $fp [get_ports { led[1] }]
+
 #puts "\nsignal_* ports quiet"
 #puts $fp "signal_* ports quiet"
 #puts $fp [get_ports -quiet signal_*]
diff --git a/design_introspection-plugin/tests/trim_name/trim_name.test.cc b/design_introspection-plugin/tests/trim_name/trim_name.test.cc
new file mode 100644
index 0000000..5da2641
--- /dev/null
+++ b/design_introspection-plugin/tests/trim_name/trim_name.test.cc
@@ -0,0 +1,22 @@
+#include "../common/utils.h"
+
+#include <gtest/gtest.h>
+
+TEST(UtilitiesTest, TrimName)
+{
+    std::string original("  wire_name  ");
+    // trim wire_name from both sides
+    std::string name(original);
+    trim(name);
+    EXPECT_EQ(name, "wire_name");
+
+    // trim wire_name from left-hand side
+    name = original;
+    trim_left(name);
+    EXPECT_EQ(name, "wire_name  ");
+
+    // trim wire_name from right-hand side
+    name = original;
+    trim_right(name);
+    EXPECT_EQ(name, "  wire_name");
+}
diff --git a/fasm-plugin/fasm.cc b/fasm-plugin/fasm.cc
index 5ab4c1a..245d4bd 100644
--- a/fasm-plugin/fasm.cc
+++ b/fasm-plugin/fasm.cc
@@ -24,7 +24,7 @@
  *   annotations on the design cells.
  */
 
-#include "../bank_tiles.h"
+#include "../common/bank_tiles.h"
 #include "kernel/log.h"
 #include "kernel/register.h"
 #include "kernel/rtlil.h"
diff --git a/xdc-plugin/xdc.cc b/xdc-plugin/xdc.cc
index 3d792dd..1e97033 100644
--- a/xdc-plugin/xdc.cc
+++ b/xdc-plugin/xdc.cc
@@ -26,7 +26,7 @@
  *   Tcl interpreter and processed by the new XDC commands imported to the
  *   Tcl interpreter.
  */
-#include "../bank_tiles.h"
+#include "../common/bank_tiles.h"
 #include "kernel/log.h"
 #include "kernel/register.h"
 #include "kernel/rtlil.h"