)]}'
{
  "commit": "e8ad82018d392d3ddf3f4f947e4a1a56e7ff1c0f",
  "tree": "11b5795efc123673eb6d8551acdffed06309b528",
  "parents": [
    "a34fb4832ffa42c738d9ff993004e24c5e8fd06a"
  ],
  "author": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Wed May 10 12:46:41 2023 +0200"
  },
  "committer": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Fri May 12 15:13:01 2023 +0200"
  },
  "message": "Add test for translate_off...translate_on sections.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4312522f0b524ff2d6a26d55b69f410feec48bf9",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/tests/Makefile",
      "new_id": "94f6563e70687d2fb4c2c4c0171c37a56815b4ed",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/tests/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d7e047898dadd6794e66e42f93f0b5e49604b24e",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/tests/translate_off/translate_off.tcl"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3ca8840eb4f9c7200f33fd15eb188ef510b94304",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/tests/translate_off/translate_off.v"
    }
  ]
}