diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index d634bb7..86e40e0 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -23,7 +23,9 @@
 
 void Clocks::AddClock(const std::string& name, std::vector<RTLIL::Wire*> wires,
                       float period, float rising_edge, float falling_edge) {
-    AddClockWires(name, wires, period, rising_edge, falling_edge);
+    std::for_each(wires.begin(), wires.end(), [&, this](RTLIL::Wire* wire) {
+	AddClock(name, wire, period, rising_edge, falling_edge);
+    });
 }
 
 void Clocks::AddClock(const std::string& name, RTLIL::Wire* wire, float period,
@@ -46,26 +48,6 @@
              clock.RisingEdge(), clock.FallingEdge());
 }
 
-void Clocks::AddClockWires(const std::string& name,
-                           std::vector<RTLIL::Wire*> wires, float period,
-                           float rising_edge, float falling_edge) {
-    std::for_each(wires.begin(), wires.end(), [&, this](RTLIL::Wire* wire) {
-	AddClockWire(name, wire, period, rising_edge, falling_edge);
-    });
-}
-
-void Clocks::AddClockWire(const std::string& name, RTLIL::Wire* wire,
-                          float period, float rising_edge, float falling_edge) {
-    auto clock =
-        std::find_if(clocks_.begin(), clocks_.end(),
-                     [&](Clock& clock) { return clock.Name() == name; });
-    if (clock == clocks_.end()) {
-	AddClock(name, wire, period, rising_edge, falling_edge);
-    } else {
-	clock->AddWire(wire);
-    }
-}
-
 std::vector<std::string> Clocks::GetClockNames() {
     std::vector<std::string> res;
     for (auto clock : clocks_) {
@@ -94,7 +76,7 @@
 	auto clock_wires = clock.GetClockWires();
 	for (auto clock_wire : clock_wires) {
 	    auto aliases = pass->FindAliasWires(clock_wire);
-	    AddClockWires(clock.Name(), aliases, clock.Period(),
+	    AddClock(clock.Name(), aliases, clock.Period(),
 	                  clock.RisingEdge(), clock.FallingEdge());
 	}
     }
@@ -106,14 +88,20 @@
 void Clocks::Propagate(BufferPropagation* pass) {
 #ifdef SDC_DEBUG
     log("Start buffer clock propagation\n");
+    log("IBUF pass\n");
 #endif
-    for (auto clock : clocks_) {
+    std::vector<Clock> clocks(clocks_);
+    for (auto clock : clocks) {
 #ifdef SDC_DEBUG
 	log("Processing clock %s\n", clock.Name().c_str());
 #endif
 	PropagateThroughBuffer(pass, clock, IBuf());
     }
-    for (auto clock : clocks_) {
+#ifdef SDC_DEBUG
+    log("BUFG pass\n");
+#endif
+    clocks = clocks_;
+    for (auto clock : clocks) {
 #ifdef SDC_DEBUG
 	log("Processing clock %s\n", clock.Name().c_str());
 #endif
@@ -200,7 +188,7 @@
       period_(period),
       rising_edge_(rising_edge),
       falling_edge_(falling_edge) {
-    AddWire(wire);
+    UpdateWires(wire);
 }
 
 Clock::Clock(const std::string& name, std::vector<RTLIL::Wire*> wires,
@@ -210,14 +198,7 @@
       rising_edge_(rising_edge),
       falling_edge_(falling_edge) {
     std::for_each(wires.begin(), wires.end(),
-                  [&, this](RTLIL::Wire* wire) { AddWire(wire); });
-}
-
-void Clock::AddWire(RTLIL::Wire* wire) {
-    auto clock_wire = std::find(clock_wires_.begin(), clock_wires_.end(), wire);
-    if (clock_wire == clock_wires_.end()) {
-	clock_wires_.push_back(wire);
-    }
+                  [&, this](RTLIL::Wire* wire) { UpdateWires(wire); });
 }
 
 void Clock::UpdateClock(RTLIL::Wire* wire, float period, float rising_edge,
diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h
index f4b0e53..faa8aec 100644
--- a/sdc-plugin/clocks.h
+++ b/sdc-plugin/clocks.h
@@ -36,7 +36,6 @@
           float rising_edge, float falling_edge);
     Clock(const std::string& name, std::vector<RTLIL::Wire*> wires,
           float period, float rising_edge, float falling_edge);
-    void AddWire(RTLIL::Wire* wire);
     std::vector<RTLIL::Wire*> GetClockWires() { return clock_wires_; }
     const std::string& Name() const { return name_; }
     float Period() { return period_; }
@@ -65,10 +64,6 @@
     void AddClock(const std::string& name, RTLIL::Wire* wire, float period,
                   float rising_edge, float falling_edge);
     void AddClock(Clock& clock);
-    void AddClockWires(const std::string& name, std::vector<RTLIL::Wire*> wires,
-                       float period, float rising_edge, float falling_edge);
-    void AddClockWire(const std::string& name, RTLIL::Wire* wire, float period,
-                      float rising_edge, float falling_edge);
     std::vector<std::string> GetClockNames();
     void Propagate(NaturalPropagation* pass);
     void Propagate(BufferPropagation* pass);