)]}'
{
  "commit": "eba2751f62b0af673955da0c3d6b6e32c6fe12cb",
  "tree": "ece7049a66be7491d8a3061ef8ca3b6f533d0eb8",
  "parents": [
    "bf5383e7d66840ee10cb4ad8377a8c2952ffa84d"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Fri Mar 24 15:41:47 2023 +0100"
  },
  "committer": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Wed Apr 05 15:57:50 2023 +0200"
  },
  "message": "systemverilog-plugin: Add simplify.h\n\nSigned-off-by: Magdalena Andrys \u003cmandrys@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5620ab9031d1d475330dd37f0519833d27aed40a",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/third_party/yosys/simplify.h"
    }
  ]
}